From bfe4b65788e9759f417723f49b07763d6175d5dc Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Tue, 5 Jun 2018 22:56:46 -0700
Subject: [PATCH] Fix a port width problem, and change file permissions.

---
 cpu.sv      | 2 +-
 memory.sv   | 4 +++-
 mux2.sv     | 0
 mux4.sv     | 0
 register.sv | 0
 5 files changed, 4 insertions(+), 2 deletions(-)
 mode change 100755 => 100644 memory.sv
 mode change 100755 => 100644 mux2.sv
 mode change 100755 => 100644 mux4.sv
 mode change 100755 => 100644 register.sv

diff --git a/cpu.sv b/cpu.sv
index 7b00976..e9c4016 100644
--- a/cpu.sv
+++ b/cpu.sv
@@ -75,7 +75,7 @@ module cpu 	(input logic clk, reset,
 	assign pc_compute = rt_val + const_val;
 
 	mux2 #(8) pc_mux(
-		.left(pc + 1),
+		.left(pc + 8'b01),
 		.right(pc_compute),
 		.select(should_jump & (inst[28] | (inst[26] ^ (rs_val == 0)))),
 		.out(pc_next));
diff --git a/memory.sv b/memory.sv
old mode 100755
new mode 100644
index 2f18366..5df46d5
--- a/memory.sv
+++ b/memory.sv
@@ -8,7 +8,9 @@ module memory #(width=32)
 		if(reset) begin
 			data <= '{default: 0};
 		end else begin
-			if(wen) data[waddr] <= in;
+			if(wen) begin 
+				data[waddr] <= in;
+			end
 		end
 	
 	assign out = data[raddr];
diff --git a/mux2.sv b/mux2.sv
old mode 100755
new mode 100644
diff --git a/mux4.sv b/mux4.sv
old mode 100755
new mode 100644
diff --git a/register.sv b/register.sv
old mode 100755
new mode 100644