module memory #(width=32)
				(input logic [7:0] raddr, waddr,
				 input logic [width-1:0] in,
				 input logic clk, wen, reset,
				 output logic [width-1:0] out);
	logic [width-1:0] data [0:255];
	always_ff@(posedge clk)
		if(reset) begin
			data <= '{default: 0};
		end else begin
			if(wen) data[waddr] <= in;
		end
	
	assign out = data[raddr];
endmodule