From 7cababbe67e35b0d8a4b46e71c84e90ae569f7ce Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Tue, 28 May 2019 22:38:23 -0700
Subject: [PATCH] fix cache using wrong LRU value.

---
 src/CacheSim/Cache.elm | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/CacheSim/Cache.elm b/src/CacheSim/Cache.elm
index 4290a41..0154989 100644
--- a/src/CacheSim/Cache.elm
+++ b/src/CacheSim/Cache.elm
@@ -67,7 +67,7 @@ findEmptySlot =
 findLruSlot : CacheSet -> Maybe Int
 findLruSlot cs =
     let
-        minLru = List.minimum <| List.map cacheSlotLru cs
+        minLru = List.maximum <| List.map cacheSlotLru cs
         isMin s = Just (cacheSlotLru s) == minLru
     in
         intMapFind isMin cs