diff --git a/HW1.tex b/HW1.tex index 636a037..a30e4fa 100644 --- a/HW1.tex +++ b/HW1.tex @@ -58,7 +58,10 @@ Not quite sure what this question means, but I have a few thoughts: 193nm light, and focused on refining the technique. \item We started to perform multiple lithography (and maybe etch) steps for a single layer, which made it possible to - halve (or further reduce) the minimum pitch. + halve (or further reduce) the minimum pitch. Exposing + photoresist more than once also made it possible (from what I can tell) to use all the special + techniques (off-axis illumination, immersion, RET), which otherwise constrain masks to being only + horizontal or only vertical. \item Self-aligned mutli-patterning techniques cannot really lay down ``holes'' in lines; these holes have to be added later. As a result, layouts of modern CPUs are very regular, @@ -71,7 +74,14 @@ Not quite sure what this question means, but I have a few thoughts: From the ``Rosetta Stone of Lithography'' it looks like with true double patterning, the smallest we can get is the 10nm node (50nm pitch). +However, the Breakfast Bytes article, right after saying 50nm is the smallest +pitch we can get with double patterning, brings up SADP, which is also +double patterning, but can go as low as 40nm. In the Rosetta Stone, +however, 40nm seems to correspond to `Higher-order pitch division', and not +double patterning, so I still think 50nm pitch / 10nm node is the answer here. + \section*{Q7} We use tin plasma! Apparently, tin is ``fairly efficient'' at converting laser light into EUV. + \end{document} diff --git a/HW2.tex b/HW2.tex new file mode 100644 index 0000000..56c2472 --- /dev/null +++ b/HW2.tex @@ -0,0 +1,46 @@ +\documentclass{article} +\usepackage[margin=1in]{geometry} +\usepackage{graphicx} +\title{Homework 2} +\begin{document} +\maketitle +\section*{Q1} +The current scales linearly with oxide capacitance per unit area, $C_{ox}$. +Doubling the thickness of the insulator is akin to doubling the distance between the two plates, +which halves $C_{ox}$. Thus, current would be halved as well. + +\section*{Q2} +This occurs, by definition, at the threshold voltage, $V_t$. + +\section*{Q3} +\begin{figure}[h] + \centering + \includegraphics[width=0.8\linewidth]{Q3.png} + \label{fig:iv} + \caption{} +\end{figure} + +\section*{Q4} +The depletion region is larger because of the potential on the drain. +Since (for an NMOS transistor) the source is tied to the lowest potential, to drive current +through the transistor, we need to apply potential to the drain. +Doing so pushes more carriers into the depletion region, causing it to grow. + +\section*{Q5} +The potential is $V_{gs} - V_t$, which is also written as $V_{GT}$ in the book. + +\section*{Q6} +The transistor in the picture likely suffers from velocity saturation. I think +so because for each step in gate voltage, the current increases by the same amount. +However, our simple models predict that this should be a quadratic increase. +This difference in behavior is typically caused by velocity saturation. + +\section*{Q7} +The transistor in the picture likely suffers from impact ionization. +I think so because at high drain-source voltages, the current starts +to "bend upwards", increasing more than it is expected to past the saturation +point. This can be caused by "hot" electrons producing electron/hole pairs +on impact with the substrate atoms. These pairs serve as carriers, thereby +contributing to increased current. + +\end{document} diff --git a/HW3.tex b/HW3.tex new file mode 100644 index 0000000..b55c29d --- /dev/null +++ b/HW3.tex @@ -0,0 +1,121 @@ +\documentclass{article} +\usepackage[margin=1in]{geometry} +\usepackage{graphicx} +\usepackage{amsmath} +\title{Homework 3} +\begin{document} +\maketitle +\section*{Q1} +Given the logical formula, we can follow +the following process to convert it into strictly +inverters, NOR, and NAND gates: + +\begin{equation*} + \begin{aligned} + & \lnot((AB+C)D+E) \\ + \Leftrightarrow & \lnot(\lnot\lnot(AB+C)D+E) & \text{(negation involutive)} \\ + \Leftrightarrow & \lnot(\lnot(\lnot(AB+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\ + \Leftrightarrow & \lnot(\lnot(\lnot(\lnot\lnot AB+C)+\lnot D)+E) & \text{(negation involutive)} \\ + \Leftrightarrow & \lnot(\lnot(\lnot(\lnot(\lnot A + \lnot B)+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\ + \end{aligned} +\end{equation*} + +This corresponds to the following circuit: + +\begin{figure}[h] + \centering + \includegraphics[width=0.7\linewidth]{Q1HW3.png} +\end{figure} + +\pagebreak +\section*{Q2} +Making Scott's adjustment (adding a top-level 'not' to the formula in the assignment) yields the following: + +\begin{figure}[h] + \centering + \includegraphics[width=0.7\linewidth]{Q2.png} +\end{figure} + +\pagebreak +\section*{Q3} +The book gives the following equation for determing the ideal number of stages: + +\begin{equation*} + \begin{aligned} + N &= \log_{\rho}F \\ + 0 &= p_\text{inv} + \rho(1-\ln\rho) + \end{aligned} +\end{equation*} + +Where $p_\text{inv}$ is the intrinsic delay of an inverter. +For $p_\text{inv} = 5$, we have $\rho = 6.14$. We then compute $F$: + +\begin{equation*} + \begin{aligned} + & F &= GBH \\ + & G &= 1 \\ + & B &= 1 \\ + & H &= 1000 \\ + \Rightarrow & F &= 1000 + \end{aligned} +\end{equation*} + +The ideal number of stages is then: + +\begin{equation*} + \log_\rho F = 3.8 \approx 4 +\end{equation*} + +For all inverters, then, we get the following: + +\begin{equation*} + \begin{aligned} + \hat{f} &= \sqrt[4]{1000} \\ + \text{sz}_4 &= 1000/\hat{f}^1 = 178 \\ + \text{sz}_3 &= 1000/\hat{f}^2 = 31.6 \\ + \text{sz}_2 &= 1000/\hat{f}^3 = 5.62 \\ + \text{sz}_1 &= 1000/\hat{f}^4 = 1 \\ + \end{aligned} +\end{equation*} + +\pagebreak +\section*{Q4} +First, to compute stage effort $\hat{f}$. + +\begin{equation*} + \begin{aligned} + & F &= GBH \\ + & G &= \left(\frac{4}{3}\right)\left(\frac{5}{3}\right)\left(\frac{5}{3}\right) \\ + & B &= 3 \\ + & H &= 1000 \\ + \Rightarrow & F &= 11111 + \end{aligned} +\end{equation*} + +Assuimng a $p_\text{invs}$ of 1, and thus $\rho = 3.59$, we get: + +\begin{equation*} + \log_\rho F = 7.2 \approx 7 +\end{equation*} + +Since we currently have 3 stages, we should insert 4 inverters. +It appears as though inserting inverters only at the end makes it +too difficult for the first-stage NAND gate to drive the 3-branched +NOR gates (we end up with an optimal size less than 1). Instead, +I will insert two inverters right after the NAND2 gate, and two more +inverters at the end. We can now compute gate sizes: + +\begin{equation*} + \begin{aligned} + \hat{f} &= \sqrt[7]{11111} \\ + \text{sz}_7 &= 1000/\hat{f}^1 = 264 \\ + \text{sz}_6 &= 1000/\hat{f}^2 = 69.8 \\ + \text{sz}_5 &= 1000/\hat{f}^3 * \left(\frac{5}{3}\right) = 30.8 \\ + \text{sz}_4 &= 1000/\hat{f}^4 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right) = 13.5 \\ + \text{sz}_3 &= 1000/\hat{f}^5 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 10.7 \\ + \text{sz}_2 &= 1000/\hat{f}^6 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 2.84 \\ + \text{sz}_1 &= 1000/\hat{f}^7 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 1 \\ + \end{aligned} +\end{equation*} + +\end{document} diff --git a/Q1HW3.png b/Q1HW3.png new file mode 100644 index 0000000..9e38637 Binary files /dev/null and b/Q1HW3.png differ diff --git a/Q2.png b/Q2.png new file mode 100644 index 0000000..6fe6eb0 Binary files /dev/null and b/Q2.png differ diff --git a/Q2.xcf b/Q2.xcf new file mode 100644 index 0000000..984320a Binary files /dev/null and b/Q2.xcf differ diff --git a/Q3.png b/Q3.png new file mode 100644 index 0000000..273be93 Binary files /dev/null and b/Q3.png differ