\documentclass{article}
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\title{Homework 3}
\begin{document}
\maketitle
\section*{Q1}
Given the logical formula, we can follow
the following process to convert it into strictly
inverters, NOR, and NAND gates:

\begin{equation*}
  \begin{aligned}
    & \lnot((AB+C)D+E) \\
      \Leftrightarrow & \lnot(\lnot\lnot(AB+C)D+E) & \text{(negation involutive)} \\
      \Leftrightarrow & \lnot(\lnot(\lnot(AB+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\
      \Leftrightarrow & \lnot(\lnot(\lnot(\lnot\lnot AB+C)+\lnot D)+E) & \text{(negation involutive)} \\
      \Leftrightarrow & \lnot(\lnot(\lnot(\lnot(\lnot A + \lnot B)+C)+\lnot D)+E) & \text{(DeMorgan's Laws)} \\
  \end{aligned}
\end{equation*}

This corresponds to the following circuit:

\begin{figure}[h]
    \centering
    \includegraphics[width=0.7\linewidth]{Q1HW3.png}
\end{figure}

\pagebreak
\section*{Q2}
Making Scott's adjustment (adding a top-level 'not' to the formula in the assignment) yields the following:

\begin{figure}[h]
    \centering
    \includegraphics[width=0.7\linewidth]{Q2.png}
\end{figure}

\pagebreak
\section*{Q3}
The book gives the following equation for determing the ideal number of stages:

\begin{equation*}
  \begin{aligned}
      N &= \log_{\rho}F \\
      0 &= p_\text{inv} + \rho(1-\ln\rho)
  \end{aligned}
\end{equation*}

Where $p_\text{inv}$ is the intrinsic delay of an inverter.
For $p_\text{inv} = 5$, we have $\rho = 6.14$. We then compute $F$:

\begin{equation*}
  \begin{aligned}
      & F &= GBH \\
      & G &= 1 \\
      & B &= 1 \\
      & H &= 1000 \\
    \Rightarrow & F &= 1000
  \end{aligned}
\end{equation*}

The ideal number of stages is then:

\begin{equation*}
  \log_\rho F = 3.8 \approx 4
\end{equation*}

For all inverters, then, we get the following:

\begin{equation*}
  \begin{aligned}
      \hat{f} &= \sqrt[4]{1000} \\
      \text{sz}_4 &= 1000/\hat{f}^1 = 178 \\
      \text{sz}_3 &= 1000/\hat{f}^2 = 31.6 \\
      \text{sz}_2 &= 1000/\hat{f}^3 = 5.62 \\
      \text{sz}_1 &= 1000/\hat{f}^4 = 1 \\
  \end{aligned}
\end{equation*}

\pagebreak
\section*{Q4}
First, to compute stage effort $\hat{f}$.

\begin{equation*}
  \begin{aligned}
      & F &= GBH \\
      & G &= \left(\frac{4}{3}\right)\left(\frac{5}{3}\right)\left(\frac{5}{3}\right) \\
      & B &= 3 \\
      & H &= 1000 \\
    \Rightarrow & F &= 11111
  \end{aligned}
\end{equation*}

Assuimng a $p_\text{invs}$ of 1, and thus $\rho = 3.59$, we get:

\begin{equation*}
  \log_\rho F = 7.2 \approx 7
\end{equation*}

Since we currently have 3 stages, we should insert 4 inverters.
It appears as though inserting inverters only at the end makes it
too difficult for the first-stage NAND gate to drive the 3-branched
NOR gates (we end up with an optimal size less than 1). Instead,
I will insert two inverters right after the NAND2 gate, and two more
inverters at the end. We can now compute gate sizes:

\begin{equation*}
  \begin{aligned}
      \hat{f} &= \sqrt[7]{11111} \\
      \text{sz}_7 &= 1000/\hat{f}^1 = 264 \\
      \text{sz}_6 &= 1000/\hat{f}^2 = 69.8 \\
      \text{sz}_5 &= 1000/\hat{f}^3 * \left(\frac{5}{3}\right) = 30.8 \\
      \text{sz}_4 &= 1000/\hat{f}^4 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right) = 13.5 \\
      \text{sz}_3 &= 1000/\hat{f}^5 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 10.7  \\
      \text{sz}_2 &= 1000/\hat{f}^6 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 2.84  \\
      \text{sz}_1 &= 1000/\hat{f}^7 * \left(\frac{5}{3}\right)\left(\frac{5}{3}\right)3 = 1  \\
  \end{aligned}
\end{equation*}

\end{document}