\documentclass{article}
\usepackage[margin=1in]{geometry}
\usepackage{graphicx}
\usepackage{amsmath}
\title{Homework 4}
\begin{document}
\maketitle
\section*{Q1}
\begin{itemize}
    \item Heat is analagous to electric charge. Much like charge flows in electircal circuits,
        from areas with higher electric potential to areas with lower electrical potential,
        heat flows from areas of higher temperature to areas of lower temperature.
    \item Thermal capacitance is analagous to electric capacitance. Much like materials of higher
        thermal capacitance take more heat to increase in temperature, materals with higher
        electrical capacitance require more charge to increase in voltage / electric potential.
    \item As hinted at in the earlier question, temperature is analagous to voltage. Differences
        in temperature / voltage cause the flow of heat / charge.
    \item Just as heat is analagous to electric charge, heat flow is analagous to current.
        Heat flow is propertional to the difference between temperature in two areas,
        and electric current is propertional to differences in voltage / electric potential.
\end{itemize}

\subsection*{Q2}
Radiation is the mode of heat transfer that occurs via EM waves. 

\subsection*{Q3}
Electrical current is easier to constrain, because we have much better electrical insulators
than we do themral insulators. It's possible to have materials with electrical insulation
much greater than $10^8$, but thermal insulation hovers in the thousands-tens of thousands range.

\section*{Q4}
We can reduce dynamic power by gating the clock signal. If we know that a circuit won't be in use for
some time, we can use an \textsc{And} gate to prevent the clock signal from propagating into the
unused part of the network. This is crucial, because the clock signal has an activity factor of $\alpha=1$,
which means that components connected to the clock cost a lot of power. Timed components for which
the clock signal has been turned off no longer switch at all, and thus do not draw or dump any power.

Supply voltage can be lowered to significantly reduce power consumption. Since power is related
quadratically to voltage, halving the supply voltage can reduce power consumption by a factor of four.
By receiving external information about the load placd on the circuit, we can dynamically reduce the power
(and slow down the circuit) at times when it's not in heavy use.

\pagebreak
\section*{Q5}
\subsection*{Minimal delay}
We are ingoring intrinsic delay. Using the book's log equation, we find:

\begin{equation*}
    \begin{aligned}
    & \rho(1-\ln \rho) = 0 \\
        \Rightarrow \quad & e = \rho \\
    \end{aligned}
\end{equation*}

Since we have $B=1$ and $H=1$, our logical effort is $G = 10,000$, we have $F = BGH = 10,000$.
The ideal number of stages is:

\begin{equation*}
    \log_\rho F = \ln F \approx 9
\end{equation*}

Then, with each of the 9 stages contributing stage contributing $10,000^{1/9}$ units of delay,
the total delay becomes:

\begin{equation*}
    9 \times 10,000^{1/9} \approx 25
\end{equation*}

\subsection*{Reducing Power Using Supply}
To reduce the power consumption by alterting supply, we need to reduce supply by a factor
of 2, since the two are quadratically related.

\subsection*{Reducing Power by Changing the Number of Stages}
The total amount of capacitance is proportional to the sum of the sizes
of the inverters in the circuit. This, in turn, is given by the geometric sequence:

\begin{equation*}
    1 + \hat{f} + \hat{f}^2 + ... + \hat{f}^{N-1} = \frac{\hat{f}^N-1}{\hat{f}-1}
\end{equation*}

Since $\hat{f} = \sqrt[N]{F}$, this simplifies to:

\begin{equation*}
    \frac{F-1}{\sqrt[n]{F}-1}
\end{equation*}

To determine the number of stages for $\frac{1}{4}$ power, we just solve:

\begin{equation*}
    \begin{aligned}
        \frac{F-1}{\sqrt[n]{F}-1} & < \frac{1}{4} \frac{F-1}{\sqrt[9]{F}-1} \\
        4(\sqrt[9]{F}-1) & < \sqrt[n]{F}-1 \\
    \end{aligned}
\end{equation*}

Solving using Wolfram Alpha, we get $n \leq 4$. This brings us to a total delay
of $4 \times 10,000^{(1/4)} = 40$.

\pagebreak
\section*{Q6}
\begin{figure}[h]
    \centering
    \includegraphics[width=0.7\linewidth]{nand.png}
    \caption{Step-up 2-input NAND gate.}
\end{figure}

\end{document}
