108 lines
4.2 KiB
TeX
108 lines
4.2 KiB
TeX
\documentclass{article}
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\usepackage[margin=1in]{geometry}
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\usepackage{graphicx}
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\usepackage{amsmath}
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\title{Homework 4}
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\begin{document}
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\maketitle
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\section*{Q1}
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\begin{itemize}
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\item Heat is analagous to electric charge. Much like charge flows in electircal circuits,
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from areas with higher electric potential to areas with lower electrical potential,
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heat flows from areas of higher temperature to areas of lower temperature.
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\item Thermal capacitance is analagous to electric capacitance. Much like materials of higher
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thermal capacitance take more heat to increase in temperature, materals with higher
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electrical capacitance require more charge to increase in voltage / electric potential.
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\item As hinted at in the earlier question, temperature is analagous to voltage. Differences
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in temperature / voltage cause the flow of heat / charge.
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\item Just as heat is analagous to electric charge, heat flow is analagous to current.
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Heat flow is propertional to the difference between temperature in two areas,
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and electric current is propertional to differences in voltage / electric potential.
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\end{itemize}
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\subsection*{Q2}
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Radiation is the mode of heat transfer that occurs via EM waves.
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\subsection*{Q3}
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Electrical current is easier to constrain, because we have much better electrical insulators
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than we do themral insulators. It's possible to have materials with electrical insulation
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much greater than $10^8$, but thermal insulation hovers in the thousands-tens of thousands range.
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\section*{Q4}
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We can reduce dynamic power by gating the clock signal. If we know that a circuit won't be in use for
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some time, we can use an \textsc{And} gate to prevent the clock signal from propagating into the
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unused part of the network. This is crucial, because the clock signal has an activity factor of $\alpha=1$,
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which means that components connected to the clock cost a lot of power. Timed components for which
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the clock signal has been turned off no longer switch at all, and thus do not draw or dump any power.
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Supply voltage can be lowered to significantly reduce power consumption. Since power is related
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quadratically to voltage, halving the supply voltage can reduce power consumption by a factor of four.
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By receiving external information about the load placd on the circuit, we can dynamically reduce the power
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(and slow down the circuit) at times when it's not in heavy use.
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\pagebreak
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\section*{Q5}
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\subsection*{Minimal delay}
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We are ingoring intrinsic delay. Using the book's log equation, we find:
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\begin{equation*}
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\begin{aligned}
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& \rho(1-\ln \rho) = 0 \\
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\Rightarrow \quad & e = \rho \\
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\end{aligned}
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\end{equation*}
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Since we have $B=1$ and $H=1$, our logical effort is $G = 10,000$, we have $F = BGH = 10,000$.
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The ideal number of stages is:
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\begin{equation*}
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\log_\rho F = \ln F \approx 9
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\end{equation*}
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Then, with each of the 9 stages contributing stage contributing $10,000^{1/9}$ units of delay,
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the total delay becomes:
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\begin{equation*}
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9 \times 10,000^{1/9} \approx 25
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\end{equation*}
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\subsection*{Reducing Power Using Supply}
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To reduce the power consumption by alterting supply, we need to reduce supply by a factor
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of 2, since the two are quadratically related.
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\subsection*{Reducing Power by Changing the Number of Stages}
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The total amount of capacitance is proportional to the sum of the sizes
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of the inverters in the circuit. This, in turn, is given by the geometric sequence:
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\begin{equation*}
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1 + \hat{f} + \hat{f}^2 + ... + \hat{f}^{N-1} = \frac{\hat{f}^N-1}{\hat{f}-1}
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\end{equation*}
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Since $\hat{f} = \sqrt[N]{F}$, this simplifies to:
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\begin{equation*}
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\frac{F-1}{\sqrt[n]{F}-1}
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\end{equation*}
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To determine the number of stages for $\frac{1}{4}$ power, we just solve:
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\begin{equation*}
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\begin{aligned}
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\frac{F-1}{\sqrt[n]{F}-1} & < \frac{1}{4} \frac{F-1}{\sqrt[9]{F}-1} \\
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4(\sqrt[9]{F}-1) & < \sqrt[n]{F}-1 \\
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\end{aligned}
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\end{equation*}
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Solving using Wolfram Alpha, we get $n \leq 4$. This brings us to a total delay
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of $4 \times 10,000^{(1/4)} = 40$.
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\pagebreak
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\section*{Q6}
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\begin{figure}[h]
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\centering
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\includegraphics[width=0.7\linewidth]{nand.png}
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\caption{Step-up 2-input NAND gate.}
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\end{figure}
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\end{document}
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