From 12856ef152ebdbec79dcd16ce22f65b04b1d556f Mon Sep 17 00:00:00 2001 From: Danila Fedorin Date: Tue, 16 Mar 2021 14:28:24 -0700 Subject: [PATCH] Use improved senseamp to strengthen performance. --- final/SRAM_bits.cir | 18 ++++++++++++++++++ final/testBuffer.cir | 12 ++++++------ 2 files changed, 24 insertions(+), 6 deletions(-) diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir index c780d90..b3249f5 100644 --- a/final/SRAM_bits.cir +++ b/final/SRAM_bits.cir @@ -145,6 +145,18 @@ Xn0 ot0 in0 ot1 eva nnd3 size ='size' Xn1 ot1 in1 ot0 eva nnd3 size ='size' .ends senseAmp +.subckt iSenseAmp ot1 ot0 in1 in0 eva size=40 +Xp1 ot1 eva vdd pp ww='size' +Xp2 ot1 ot0 vdd pp ww='size' +Xp3 ot0 eva vdd pp ww='size' +Xp4 ot0 ot1 vdd pp ww='size' +Xn1 ot1 ot0 nn1 nn ww='size' +Xn2 ot0 ot1 nn0 nn ww='size' +Xn3 nn1 in1 pd nn ww='size' +Xn4 nn0 in0 pd nn ww='size' +Xn5 pd eva gnd nn ww='size' +.ends + .subckt precharge charge rwtb clk diib Xrdi rdi rwtb diib nnd2 Xnn chargeb clk rdi nnd2 @@ -193,6 +205,12 @@ Xinv triggerb trigger inv size='40' Xamp set rst btt bff triggerb senseAmp size='200' .ends read1 +.subckt iReadSub btt bff set rst rwt clk en +Xnd trigger rwt en clk nnd3 +Xinv triggerb trigger inv size='40' +Xamp set rst btt bff triggerb iSenseAmp size='200' +.ends read1 + .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 Xset01 set01 set0 set1 nnd2 Xset23 set23 set2 set3 nnd2 diff --git a/final/testBuffer.cir b/final/testBuffer.cir index f6dec06..e2e484c 100644 --- a/final/testBuffer.cir +++ b/final/testBuffer.cir @@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5' *********begin: topLevel***** -.param per = 1.3ns +.param per = 1.2ns .param dataLead=per*0.1 .param lw=2000 .param wirew=8 @@ -30,8 +30,8 @@ vdd vdd 0 'supply' Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300 Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300 -Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=300 -Xdii din dat1 period='per' start='per' total=4 duty=2 sz=300 +Xrdwr rdw dat1 period='2*per' start='2*per' total=2 duty=1 sz=300 +Xdii din dat1 period='2*per' start='per' total=4 duty=2 sz=300 Xad adf ad clk flop Xdinff dinf din clk flop @@ -39,7 +39,7 @@ Xrdwff rdwf rdw clk flop Xrotff dotf dot clk flop Xdec choose adf clk decModel -Xwr bf3 bt3 din rdw clk write1 +Xwr bt3 bf3 din rdw clk write1 Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew' Xmd1 bt2 bf2 memLoad number=15 Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew' @@ -49,12 +49,12 @@ Xmd3 bt4 bf4 memLoad number=16 Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xmd4 btt bff memLoad number =16 Xla bt1 bf1 choose mem1 -Xrd btt bff set rst rdwf clk choose readSub +Xrd btt bff set rst rdwf clk choose iReadSub Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect .ic V(la:tt)=0 V(la:ff)=1 .ic V(bt2)=1 -.tran 1p 'per*40' +.tran 1p 'per*20' .meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1