diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir
index 839dcd5..90a7e02 100644
--- a/final/SRAM_bits.cir
+++ b/final/SRAM_bits.cir
@@ -41,8 +41,8 @@ Xf lf rf wire len='len' wid='wid'
 .subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10
 Xt lt rt wire len='len' wid='wid'
 Xf lf rf wire len='len' wid='wid'
-Xpt rt clk vdd pp ww='ww*4'
-Xpf rf clk vdd pp ww='ww*4'
+Xpt rt clk vdd pp ww='ww*2'
+Xpf rf clk vdd pp ww='ww*2'
 .ends
 
 .subckt nn d g s  ww=100
diff --git a/final/testBuffer.cir b/final/testBuffer.cir
index 6de315d..08d548b 100644
--- a/final/testBuffer.cir
+++ b/final/testBuffer.cir
@@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
 
 
 *********begin: topLevel*****
-.param per = 1.35ns
+.param per = 1.33ns
 .param dataLead=per*0.1
 .param lw=2000
 .param wirew=14
@@ -30,8 +30,8 @@ vdd vdd 0 'supply'
 
 Xclok clk               dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
 Xad ad               dat1 period='per' start='per' total=1 duty=0.5 sz=300
-Xrdwr rdw               dat1 period='per' start='2*per'        total=2 duty=1 sz=300
-Xdii din                dat1 period='per' start='per'          total=4 duty=2 sz=300
+Xrdwr rdw               dat1 period='3*per' start='2*per'        total=2 duty=1 sz=300
+Xdii din                dat1 period='3*per' start='per'          total=4 duty=2 sz=300
 
 Xinv1 clkb1 clk inv
 Xinv2 clkb2 clkb1 inv