From 8ba9d02a8eac47a94bdd373e6c37a31b7916c987 Mon Sep 17 00:00:00 2001 From: Danila Fedorin Date: Mon, 15 Mar 2021 16:02:04 -0700 Subject: [PATCH] 1.24ns --- final/SRAM_bits.cir | 2 +- final/testBuffer.cir | 18 +++++++++--------- 2 files changed, 10 insertions(+), 10 deletions(-) diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir index 299d3e4..70788cb 100644 --- a/final/SRAM_bits.cir +++ b/final/SRAM_bits.cir @@ -190,7 +190,7 @@ Xh2 nn1 dot inv .subckt readSub btt bff set rst rwt clk en Xnd trigger rwt clk en nnd3 Xinv triggerb trigger inv size='40' -Xamp set rst btt bff triggerb senseAmp size='200' +Xamp set rst btt bff triggerb senseAmp size='80' .ends read1 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 diff --git a/final/testBuffer.cir b/final/testBuffer.cir index 0b43623..fc16b93 100644 --- a/final/testBuffer.cir +++ b/final/testBuffer.cir @@ -21,24 +21,24 @@ Xnf fff gnd dead nn ww='number*5' *********begin: topLevel***** -.param per = 1.3ns +.param per = 1.24ns .param dataLead=per*0.1 -.param lw=1800 -.param wirew=12 +.param lw=2000 +.param wirew=8 vdd vdd 0 'supply' -Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50 -Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=100 -Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=100 -Xdii din dat1 period='per' start='per' total=4 duty=2 sz=100 +Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=200 +Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=200 +Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=200 +Xdii din dat1 period='per*2' start='per' total=4 duty=1 sz=200 Xad adf ad clk flop Xdinff dinf din clk flop Xrdwff rdwf rdw clk flop Xdec choose adf clk decModel -Xwr bt3 bf3 din rdw clk write1 +Xwr bt3 bf3 din rdwf clk write1 Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew' Xmd1 bt2 bf2 memLoad number=15 Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew' @@ -48,7 +48,7 @@ Xmd3 bt4 bf4 memLoad number=16 Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xmd4 btt bff memLoad number =16 Xla bt1 bf1 choose mem1 -Xrd btt bff set rst rdw clk choose readSub +Xrd btt bff set rst rdwf clk choose readSub Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect .ic V(la:tt)=0 V(la:ff)=1