diff --git a/Lab1.png b/Lab1.png deleted file mode 100644 index 1eafe13..0000000 Binary files a/Lab1.png and /dev/null differ diff --git a/Lab1.xml b/Lab1.xml deleted file mode 100644 index dc6d5fe..0000000 --- a/Lab1.xml +++ /dev/null @@ -1 +0,0 @@ -7VtZj9o8FP01PE7lbCbzyGxd1E2i6ve1byZxglsT02AG6K+vQ2yy2ECqJkAbMtIovt7ic27O9RIGzv1s/TJF8+k7FmI6sEG4HjgPA9v2oSf+Z4ZNbnA9mBvilIS5ySoMY/ITSyOQ1iUJ8aJSkDNGOZlXjQFLEhzwig2lKVtVi0WMVnudoxhrhnGAqG79j4R8KoflgcL+CpN4qnq2gMyZIVVYGhZTFLJVyeQ8Dpz7lDGe383W95hm2Clc8npPe3J3D5bihDep4D+vXn/7FMbrrz9uRj+TOHoD8Y1s5RnRpRywfFi+UQikbJmEOGsEDJy71ZRwPJ6jIMtdCcqFbcpnVKQscRsRSu8ZZem2rhN52Z+wL3jKvuNSDtxeWQ2W8JI9v7IaCq6sV/mUOOV4vXf41g5U4YyYzTBPN6KIqqB4kI5ouzK9KmiFyjYtU6oqIulK8a7tAm1xIwH/DfDtjsGPIjsITOCHcAI92BKu8DiuHjTg6ncFq9syrBVPrGEcIuxHRoxh4ONJdDqMfQPEblcQe/8cxLtX/1Ighv8cxI5/HOKd2J4EY/+EGGMr9PDQhPEtHDqoJTW261HO0TF2jVGuK4yttqPcQUf2ARg6JpBHHgAu0Ocb0fZqCfy6htgGBz8t+E5vwPfAxYF/SgkH26ul6UZNqHfpsogYkISdITn8S5GE8NKQPGXIsybIwrZJEACAj6OnbgWhPqPbTaKPzOi6W+61vdi+XOzrC5bzY2+ahUAqur0LybO4jbPb+c1q21aeIToq5WlUCXR4jY8K1AlLcI0XaUKUxIlIBgJNLOx3GdYkQHQkM2YkDLNujA5QdZG2t0nc+gTytplidcecaQqjMZcM7Lsrb2XevHPzZtqGufJ2bK51ft5MeztX3o7N7M7Pm68hj8MYj2WSpXzKYpYg+lhYaxgVZd4yNpdkfcOcb+S5DFpyVqVSoJVu/s/qv/BU8otsbpt4WFdSmwoD2QMexl+Mhy3TAB8auFwccJTGmB8o6JsJTTFFnDxXH6R9evQlzJh8UK/QYjlR749deq1K5p68VvUwZp19+nHbRA4/MrpZEEoCJoQRqAKTtGCvx1KpcXpuqXRMi4G6dibhKDs+zjClaLEgQU341oSXdE+kvpRyCtXLEkr0LkEsbxuKZb5zqHNaPtUzcKZsjUVV9vCRETGU/UcFXs0X8oHKWoU7aA25Tq0hUGsoB0JraOtXu2H/gas12IDtvavZV1drw9UaTdzHOW3205gk32/eYY6yhgVq4DNBvQ5TTn3PytLDlGX6kKG7ONXgAKFT8bAq0lEoSffioZz5uHjAq3i0IR4NTli6jVN/gasNr67WhquZjqC0OFWKTD2OSa5V5Wpo+GbxpBHJtBrux3RWue1RmdhH6Xlkwhq2JBPaZ7Ady4TaEbi62oGItGdL8+pqv+dqpoN5LSK9fP/Q61ikfRVk+rTwlMHINW3jabR9WPL5kveaOe0rpO6YE8niFy35+1n8LMh5/AU= \ No newline at end of file diff --git a/Lab1/Lab1.jelib b/Lab1/Lab1.jelib new file mode 100644 index 0000000..2cf366a --- /dev/null +++ b/Lab1/Lab1.jelib @@ -0,0 +1,115 @@ +# header information: +HLab1|9.07 + +# Views: +Vlayout|lay +Vschematic|sch + +# Cell Nand2;1{lay} +CNand2;1{lay}||mocmos|1610136809876|1610479742026||DRC_last_good_drc_area_date()G1610138667832|DRC_last_good_drc_bit()I18|DRC_last_good_drc_date()G1610138667832 +Ngeneric:Facet-Center|art@0||0|0||||AV +NMetal-1-P-Active-Con|contact@0||-6|7|5||R| +NMetal-1-P-Active-Con|contact@1||-15|7|5||R| +NMetal-1-P-Active-Con|contact@2||3|7|5||R| +NMetal-1-Metal-2-Con|contact@3||-15|11.5|||| +NMetal-1-Metal-2-Con|contact@4||3|11.5|||| +NMetal-1-N-Active-Con|contact@5||-13|-40.5|5||R| +NMetal-1-N-Active-Con|contact@6||0.5|-40.5|5||R| +NMetal-1-Metal-2-Con|contact@7||14|4|||| +NMetal-1-Metal-2-Con|contact@8||-6|4|||| +NMetal-1-Metal-2-Con|contact@9||14|-37|||| +NMetal-1-Metal-2-Con|contact@10||0.5|-37|||| +NMetal-1-Polysilicon-1-Con|contact@11||-10.5|-4|||| +NMetal-1-Polysilicon-1-Con|contact@12||-1.5|-4|||| +NMetal-1-Polysilicon-1-Con|contact@13||-10.5|-30|||| +NMetal-1-Polysilicon-1-Con|contact@15||-1.5|-30|||| +NMetal-1-Polysilicon-1-Con|contact@16||-1.5|-30|||| +NN-Transistor|nmos@4||-9|-40.5|7||R| +NN-Transistor|nmos@5||-3.5|-40.5|7||R| +NMetal-2-Pin|pin@0||10|4|||| +NMetal-2-Pin|pin@1||9|-37|||| +NPolysilicon-1-Pin|pin@2||-3|-30|||| +NPolysilicon-1-Pin|pin@3||-9|-30.5|||| +NPolysilicon-1-Pin|pin@4||-3.5|-30|||| +NPolysilicon-1-Pin|pin@5||-10.5|-30.5|||| +Nartwork:Pin|pin@6||-24.5|-43.5|1|1|| +Nartwork:Pin|pin@7||12.5|-43.5|1|1|| +NP-Transistor|pmos@0||-10.5|7|7||R| +NP-Transistor|pmos@1||-1.5|7|7||R| +AP-Active|net@0|||S1800|contact@0||-5.5|6.5|pmos@1|diff-top|-5.25|6.5 +AP-Active|net@1|||S0|contact@0||-5.5|6.5|pmos@0|diff-bottom|-6.75|6.5 +AP-Active|net@2|||S1800|contact@1||-15|7|pmos@0|diff-top|-14.25|7 +AP-Active|net@3|||S0|contact@2||3|7|pmos@1|diff-bottom|2.25|7 +AMetal-2|net@4|||S1800|contact@3||-15|11.5|contact@4||3|11.5 +AMetal-1|net@5|||S2700|contact@1||-15|7|contact@3||-15|11.5 +AMetal-1|net@6|||S2700|contact@2||3|7|contact@4||3|11.5 +AMetal-2|net@11||1|S0|contact@7||14|4|pin@0||10|4 +AMetal-2|net@12||1|S0|pin@0||10|4|contact@8||-6|4 +AMetal-1|net@13||1|S900|contact@0||-6|7|contact@8||-6|4.5 +AMetal-2|net@14||1|S0|contact@9||14|-37|pin@1||9|-37 +AMetal-2|net@15||1|S0|pin@1||9|-37|contact@10||0.5|-37 +AMetal-1|net@16||1|S2700|contact@6||0.5|-40|contact@10||0.5|-37 +APolysilicon-1|net@18|||S900|pmos@1|poly-left|-1.5|0|contact@12||-1.5|-4 +APolysilicon-1|net@19|||S900|pmos@0|poly-left|-10.5|0|contact@11||-10.5|-4.5 +APolysilicon-1|net@22|||S1800|pin@2||-3|-30|contact@15||-1|-30 +AMetal-1|net@23||1|S2700|contact@13||-10.5|-30|contact@11||-10.5|-4 +AMetal-1|net@24||1|S2700|contact@15||-1.5|-30|contact@12||-1.5|-4 +AN-Active|net@25|||S0|nmos@4|diff-bottom|-5.25|-40|nmos@5|diff-top|-7.25|-40 +AN-Active|net@26|||S1800|contact@5||-13|-40.5|nmos@4|diff-top|-12.75|-40.5 +AN-Active|net@27|||S0|contact@6||0.5|-40|nmos@5|diff-bottom|0.25|-40 +APolysilicon-1|net@28|||S2700|nmos@4|poly-right|-9|-33.5|pin@3||-9|-30.5 +APolysilicon-1|net@29|||S2700|nmos@5|poly-right|-3.5|-33.5|pin@4||-3.5|-30 +APolysilicon-1|net@30|||S0|pin@3||-9|-30.5|pin@5||-10.5|-30.5 +APolysilicon-1|net@31||3|S900|contact@13||-10.5|-30|pin@5||-10.5|-30.5 +APolysilicon-1|net@32|||S1800|pin@4||-3.5|-30|contact@16||-1.5|-30 +AMetal-1|net@33|||S2700|contact@15||-1.5|-30|contact@16||-1.5|-30 +AMetal-1|net@34||1|S2700|contact@9||14|-37|contact@7||14|4 +Aartwork:Solid|net@35|||FS0|pin@7||12.5|-43.5|pin@6||-24.5|-43.5 +EI1||D5G2;|contact@11||I +EI2||D5G2;|contact@15||I +EO||D5G2;|contact@7||O +EGND|gnd|D5G2;|contact@5||G +EVdd|vdd|D5G2;|contact@3||P +X + +# Cell Nand2;1{sch} +CNand2;1{sch}||schematic|1610136165903|1610285745086| +Ngeneric:Facet-Center|art@0||0|0||||AV +NOff-Page|conn@0||-25|-0.5|||| +NOff-Page|conn@1||-18.5|-0.5|||| +NOff-Page|conn@2||3.5|-0.5|||| +NGround|gnd@0||-5.5|-15|||| +NTransistor|nmos@2||-7.5|-3.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S10 +NTransistor|nmos@3||-7.5|-9.5|||R||ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S10 +NWire_Pin|pin@3||-5.5|5|||| +NWire_Pin|pin@6||-16.5|-3.5|||| +NWire_Pin|pin@7||-16.5|2.5|||| +NWire_Pin|pin@8||-23|3|||| +NWire_Pin|pin@9||-23|-9.5|||| +NWire_Pin|pin@10||-5.5|-0.5|||| +NWire_Pin|pin@11||-9|-0.5|||| +NTransistor|pmos@0||-11|3|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S10 +NTransistor|pmos@1||-7.5|2.5|||R|2|ATTR_length(D5G0.5;X-0.5;Y-1;)S2|ATTR_width(D5G1;X0.5;Y-1;)S10 +NPower|pwr@0||-5.5|14|||| +Awire|net@6|||900|pwr@0||-5.5|14|pin@3||-5.5|5 +Awire|net@7|||1800|pmos@0|d|-9|5|pin@3||-5.5|5 +Awire|net@13|||900|conn@1|y|-16.5|-0.5|pin@6||-16.5|-3.5 +Awire|net@14|||0|nmos@2|g|-8.5|-3.5|pin@6||-16.5|-3.5 +Awire|net@15|||2700|conn@1|y|-16.5|-0.5|pin@7||-16.5|2.5 +Awire|net@16|||1800|pin@7||-16.5|2.5|pmos@1|g|-8.5|2.5 +Awire|net@17|||2700|conn@0|y|-23|-0.5|pin@8||-23|3 +Awire|net@18|||1800|pin@8||-23|3|pmos@0|g|-12|3 +Awire|net@19|||900|conn@0|y|-23|-0.5|pin@9||-23|-9.5 +Awire|net@20|||1800|pin@9||-23|-9.5|nmos@3|g|-8.5|-9.5 +Awire|net@22|||900|pmos@1|s|-5.5|0.5|pin@10||-5.5|-0.5 +Awire|net@23|||900|pin@10||-5.5|-0.5|nmos@2|d|-5.5|-1.5 +Awire|net@24|||1800|pin@10||-5.5|-0.5|conn@2|a|1.5|-0.5 +Awire|net@25|||900|pmos@0|s|-9|1|pin@11||-9|-0.5 +Awire|net@26|||0|pin@10||-5.5|-0.5|pin@11||-9|-0.5 +Awire|net@27|||900|nmos@3|s|-5.5|-11.5|gnd@0||-5.5|-13 +Awire|net@29|||900|nmos@2|s|-5.5|-5.5|nmos@3|d|-5.5|-7.5 +Awire|net@30|||900|pin@3||-5.5|5|pmos@1|d|-5.5|4.5 +EI1||D5G2;|conn@0|a|I +EI2||D5G2;|conn@1|a|I +EO||D5G2;|conn@2|a|O +X diff --git a/Lab1Detail.png b/Lab1/Lab1Detail.png similarity index 100% rename from Lab1Detail.png rename to Lab1/Lab1Detail.png diff --git a/Lab1Detail.xml b/Lab1/Lab1Detail.xml similarity index 100% rename from Lab1Detail.xml rename to Lab1/Lab1Detail.xml diff --git a/Lab1/lab1.tex b/Lab1/lab1.tex new file mode 100644 index 0000000..1a8c923 --- /dev/null +++ b/Lab1/lab1.tex @@ -0,0 +1,28 @@ +\documentclass{article} +\usepackage[margin=1in]{geometry} +\usepackage{graphicx} +\begin{document} +\section*{Lab 1} +In my drawing (figure \ref{fig:lab1}), I drew a few of the details mentioned in Chapter 3 of the textbook. +A few clarifying notes: + +\begin{itemize} + \item I included the shallow and deep n+ wells, and the SiN spacers that were + used to create them. According to the book, the shallow n+ wells help prevent + hot electron damage and reduce short channel effects. However, the deeper + wells are used to reduce resistance. + \item I also added the silicide layer, which is used, from my understanding, + to improve the conduactance of the transistor terminals. This layer + is drawn in purple. + \item I drew the the vias as metal 1 (solid blue). Electric colors them black, + and apparently, tungsten is occasionally used to ensure better connections + of the vias themselves. +\end{itemize} + +\begin{figure}[h] + \centering + \includegraphics[width=0.8\linewidth]{Lab1Detail.png} + \caption{Drawing of cross section specified in Electric Lab.} + \label{fig:lab1} +\end{figure} +\end{document}