From b58f4df33ef86ede2e7f88dd6b4b5dfbf1cf9eea Mon Sep 17 00:00:00 2001 From: Danila Fedorin Date: Tue, 9 Mar 2021 19:15:07 -0800 Subject: [PATCH] Add my initial definitions of SRAM bits. --- final/SRAM_bits.cir | 242 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 242 insertions(+) create mode 100644 final/SRAM_bits.cir diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir new file mode 100644 index 0000000..f12adcc --- /dev/null +++ b/final/SRAM_bits.cir @@ -0,0 +1,242 @@ +* This file contains all the subcircuits to be used in SRAM256.cir + +***** long channel VTP = -0.9, VTN = 0.8 ***** +*.include modelcard/1um.pm +*.param supply = 5 +*.param ll = 1u + +****** 50nm models*** + + +.include ./modelcard/50nm.pm +.param supply =1 + +.param lambda=25nm +.param ll='2*lambda' + +****** 16nm low power models*** +*.include ./modelcard/PTM_LP/16nm.pm +*.param supply =0.9 +*.param ll=16nm + +****** 16nm high peformance models*** +*.include ./modelcard/PTM_HP/16nm.pm +*.param supply =0.7 +*.param ll=16nm + + +.subckt wire iot iof len=10 wid=10 +.param rr=0.8 +.param cc = '200e-15' +rt iot iof 'rr*len*50/(wid)' +cf iof 0 'cc*len*wid*50/1e6' + +.ends + +.subckt wire_dual lt rt lf rf len=10 wid=10 +Xt lt rt wire len='len' wid='wid' +Xf lf rf wire len='len' wid='wid' +.ends + +.subckt nn d g s ww=100 +mnfet d g s 0 nmos L=ll w='ww*ll' +.ends + +.subckt pp d g s ww=100 +mpfet d g s vdd pmos L=ll w='ww*ll' +.ends + + +.subckt inv out inn size=30 beta=2 +XPP out inn vdd pp ww='size*beta/(beta+1)' +XNN out inn gnd nn ww='size/(beta+1)' +.ends + +.subckt nnd2 out in1 in0 size=30 beta=2 +Xap0 out in0 vdd pp ww='beta*size/(beta+2)' +Xap1 out in1 vdd pp ww='beta*size/(beta+2)' +Xan0 out in0 nng nn ww='2*size/(beta+2)' +Xan1 nng in1 0 nn ww='2*size/(beta+2)' +.ends nnd2 + +.subckt nor2 out in1 in0 size=30 beta=2 +Xap0 ppi in0 vdd pp ww='2*beta*size/(2*beta+1)' +Xap1 out in1 ppi pp ww='2*beta*size/(2*beta+1)' +Xan0 out in0 0 nn ww='1*size/(2*beta+1)' +Xan1 out in1 0 nn ww='1*size/(2*beta+1)' +.ends nor2 + +.subckt latch out inn clk clb size=15 beta=2 +Xn inn clk qin nn ww='5' +Xp inn clb qin pp ww='10' + +Xfp qin ggg vdd pp ww='5' +Xfn qin ggg gnd nn ww='5' + +Xi ggg qin inv size='size' +Xo out ggg inv size='3*size' +.ends latch + +.subckt flop qqq ddd clk +Xinve clb clk inv +Xflip int ddd clb clk latch +Xflop qqq int clk clb latch +.ends flop + +.subckt reg8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 clk +x7 ot7 in7 clk flop +x6 ot6 in6 clk flop +x5 ot5 in5 clk flop +x4 ot4 in4 clk flop +x3 ot3 in3 clk flop +x2 ot2 in2 clk flop +x1 ot1 in1 clk flop +x0 ot0 in0 clk flop +.ends reg8 + +.subckt dat1 out period=1ns start=1ns sz=50 total=5 duty=3 +V0 j0 0 PULSE('supply' 0 'start' 10p 10p 'duty*period-10ps' 'total*period') +x7 out j0 inv size='sz' +.ends dat1 + +*generates different data stream on all eight channels, buffered output +.subckt dat8 o7 o6 o5 o4 o3 o2 o1 o0 per=1ns start=1ns size=50 +V0 j0 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' 'per') +V1 j1 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '2*per') +V2 j2 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '3*per') +V3 j3 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '4*per') +V4 j4 0 PULSE('supply' 0 'start' 10p 10p '0.5*per-10ps' '1*per') +V5 j5 0 PULSE('supply' 0 'start' 10p 10p '1*per-10ps' '2*per') +V6 j6 0 PULSE('supply' 0 'start' 10p 10p '1.5*per-10ps' '3*per') +V7 j7 0 PULSE('supply' 0 'start' 10p 10p '2*per-10ps' '4*per') +xb o7 o6 o5 o4 o3 o2 o1 o0 j7 j6 j5 j4 j3 j2 j1 j0 buf8 sz='size' +.ends dat8 + +.subckt buf8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 sz=100 +x7 ot7 in7 inv size='sz' +x6 ot6 in6 inv size='sz' +x5 ot5 in5 inv size='sz' +x4 ot4 in4 inv size='sz' +x3 ot3 in3 inv size='sz' +x2 ot2 in2 inv size='sz' +x1 ot1 in1 inv size='sz' +x0 ot0 in0 inv size='sz' +.ends buf8 + + +.subckt nnd3 out in2 in1 in0 size=20 beta=2 +Xp0 out in0 vdd pp ww='beta*size/(beta+3)' +Xp1 out in1 vdd pp ww='beta*size/(beta+3)' +Xp2 out in2 vdd pp ww='beta*size/(beta+3)' +Xn0 out in0 nn0 nn ww='3*size/(beta+3)' +Xn1 nn0 in1 nn1 nn ww='3*size/(beta+3)' +Xn2 nn1 in2 gnd nn ww='3*size/(beta+3)' +.ends + +.subckt senseAmp ot1 ot0 in1 in0 eva size=40 +Xn0 ot0 in0 ot1 eva nnd3 size ='size' +Xn1 ot1 in1 ot0 eva nnd3 size ='size' +.ends senseAmp + + +.subckt write1 btt bff dii rwt clk +* TODO: sizes +Xclk clkb clk inv +Xdii diib dii inv +Xrwn dorw clkb rwt nor2 +Xng pd dorw gnd nn ww='10' +Xngt btt dii pd nn ww='10' +Xngf bff diib pd nn ww='10' +Xpct btt dorw vdd pp ww='10' +Xpcf bff dorw vdd pp ww='10' +.ends write1 + + + +.subckt read1 btt bff dot rwt clk +Xnd trigger rwt clk nnd2 +Xinv triggerb trigger inv +Xamp set reset btt bff triggerb senseAmp size='200' +Xinv1 set1 set inv +Xinv2 set2 set1 inv +Xinv3 reset1 reset inv +* Old setup: +* Xp nn1 set2 vdd pp +* Xn nn1 reset1 gnd nn +* Xh1 dot nn1 inv +* Xh2 nn1 dot inv +Xp dot set2 vdd pp +Xn dot reset1 gnd nn +Xh1 dot nn1 inv +Xh2 nn1 dot inv +.ends read1 + +.subckt readSub btt bff set rst rwt clk +Xnd trigger rwt clk nnd2 +Xinv triggerb trigger inv +Xamp set rst btt bff triggerb senseAmp size='200' +.ends read1 + +.subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3 +Xset01 set01 set0 set1 nnd2 +Xset23 set23 set2 set3 nnd2 +Xrst01 rst01 rst0 rst1 nnd2 +Xrst23 rst23 rst2 rst3 nnd2 +Xnset01 nset01 set01 inv +Xnset23 nset23 set23 inv +Xp01 dot nset01 vdd pp +Xp23 dot nset23 vdd pp +Xn01 dot rst01 gnd nn +Xn23 dot rst23 gnd nn +Xh1 dot nn1 inv +Xh2 nn1 dot inv +.ends readCollect + + +.subckt decode2 o11 o10 o01 o00 di1 di0 df1 df0 + +.ends + + +.subckt decode_nor16 + +.ends + +.subckt decode_nnd16 + +.ends + + +.subckt decode_16and1 + +.ends decode_16and1 + + +.subckt dmux256 o255 o223 0012 o001 dt7 dt6 dt5 d4 dt3 dt1 dt0 + +.ends dmux256 + + +.subckt decModel choose din clk size='20' +Xi1 nn1 din inv size='size' +* Here: stopped using i1 and just used din +Xnal ww1 gnd din nnd2 size='size' +Xnar nn2 vdd din nnd2 size='size' +Xnrl ww2 nn2 vdd nor2 size='size*3' +Xnrr nn3 nn2 gnd nor2 size='size' +Xna2l ww3 gnd nn3 nnd2 size='size*15' +Xna2r nn4 vdd nn3 nnd2 size='size' +Xi2 nn5 nn4 inv size='size' +Xnac nn6 nn5 clk nnd2 size='size' +Xi3 choose nn6 inv size='size' +.ends + +.subckt mem1 bt bf ope +Xpt tt ff vdd pp ww='5' +Xnt tt ff gnd nn ww='5' +Xpf ff tt vdd pp ww='5' +Xnf ff tt gnd nn ww='5' +Xat bt ope tt nn ww='5' +Xaf bf ope ff nn ww='5' +.ends +