From ca72f3eb3da3e5deb4f935b65a2e7e54e402843f Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Tue, 16 Mar 2021 12:22:50 -0700
Subject: [PATCH] Rollback to 1.3ns and no write flops.

---
 final/SRAM_bits.cir  | 18 +++++++++---------
 final/testBuffer.cir |  6 +++---
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir
index 70788cb..c780d90 100644
--- a/final/SRAM_bits.cir
+++ b/final/SRAM_bits.cir
@@ -41,8 +41,8 @@ Xf lf rf wire len='len' wid='wid'
 .subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10
 Xt lt rt wire len='len' wid='wid'
 Xf lf rf wire len='len' wid='wid'
-Xpt rt clk vdd pp ww='ww'
-Xpf rf clk vdd pp ww='ww'
+Xpt rt clk vdd pp ww='ww*4'
+Xpf rf clk vdd pp ww='ww*4'
 .ends
 
 .subckt nn d g s  ww=100
@@ -163,8 +163,8 @@ Xwt btt dorw pdt nn ww='30'
 Xwf bff dorw pdf nn ww='30'
 Xpcet pcet rwtb clk diib precharge
 Xpcef pcef rwtb clk dii precharge
-Xpct btt clk vdd pp ww='10'
-Xpcf bff clk vdd pp ww='10'
+Xpct btt clk vdd pp ww='30'
+Xpcf bff clk vdd pp ww='30'
 .ends write1
 
 
@@ -172,7 +172,7 @@ Xpcf bff clk vdd pp ww='10'
 .subckt read1 btt bff dot rwt clk
 Xnd trigger rwt clk nnd2
 Xinv triggerb trigger inv
-Xamp set reset btt bff triggerb senseAmp size='200'
+Xamp set reset btt bff triggerb senseAmp size='40'
 Xinv1 set1 set inv
 Xinv2 set2 set1 inv
 Xinv3 reset1 reset inv
@@ -188,9 +188,9 @@ Xh2 nn1 dot inv
 .ends read1
 
 .subckt readSub btt bff set rst rwt clk en
-Xnd trigger rwt clk en nnd3
+Xnd trigger rwt en clk nnd3
 Xinv triggerb trigger inv size='40'
-Xamp set rst btt bff triggerb senseAmp size='80'
+Xamp set rst btt bff triggerb senseAmp size='200'
 .ends read1
 
 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3
@@ -204,8 +204,8 @@ Xp01 nn1 nset01 vdd pp
 Xp23 nn1 nset23 vdd pp
 Xn01 nn1 rst01 gnd nn
 Xn23 nn1 rst23 gnd nn
-Xh1 dot nn1 inv
-Xh2 nn1 dot inv
+Xh1 dot nn1 inv size='60'
+Xh2 nn1 dot inv size='60'
 .ends readCollect
 
 
diff --git a/final/testBuffer.cir b/final/testBuffer.cir
index 19ed6fc..f6dec06 100644
--- a/final/testBuffer.cir
+++ b/final/testBuffer.cir
@@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
 
 
 *********begin: topLevel*****
-.param per = 2.6ns
+.param per = 1.3ns
 .param dataLead=per*0.1
 .param lw=2000
 .param wirew=8
@@ -39,7 +39,7 @@ Xrdwff rdwf rdw clk flop
 Xrotff dotf dot clk flop
 Xdec choose adf clk decModel
 
-Xwr bt3 bf3 dinf rdwf clk write1
+Xwr bf3 bt3 din rdw clk write1
 Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
 Xmd1 bt2 bf2 memLoad number=15
 Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'
@@ -54,7 +54,7 @@ Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
 
 .ic V(la:tt)=0 V(la:ff)=1
 .ic V(bt2)=1
-.tran 1p 'per*20'
+.tran 1p 'per*40'
 .meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1