From d8f4a272e308b36750269d1ed563a2d183107d03 Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Wed, 17 Mar 2021 13:07:33 -0700
Subject: [PATCH] Update to use new wire model's characteristics.

---
 final/testBuffer.cir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/final/testBuffer.cir b/final/testBuffer.cir
index c7bebb5..cfe58e8 100644
--- a/final/testBuffer.cir
+++ b/final/testBuffer.cir
@@ -21,10 +21,10 @@ Xnf fff gnd dead nn ww='number*5'
 
 
 *********begin: topLevel*****
-.param per = 1.9ns
+.param per = 1.3ns
 .param dataLead=per*0.1
 .param lw=2200
-.param wirew=12
+.param wirew=14
 
 vdd vdd 0 'supply'
 
@@ -46,7 +46,7 @@ Xrdwff rdwf rdw clk flop
 Xrotff dotf dot clk flop
 Xdec choose adf clk decModel
 
-Xwr bt3 bf3 dinf rdwf clkb6 iWrite1
+Xwr bt3 bf3 dinf rdwf adf clkb6 iWrite1
 Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
 Xmd1 bt2 bf2 memLoad number=15
 Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'