From f289e8438971c4b5f6911e3c39ea817f65d3baa9 Mon Sep 17 00:00:00 2001 From: Danila Fedorin Date: Sun, 14 Mar 2021 21:13:43 -0700 Subject: [PATCH] Current best effort. --- final/SRAM_bits.cir | 4 ++-- final/testBuffer.cir | 13 ++++++------- 2 files changed, 8 insertions(+), 9 deletions(-) diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir index 292262d..557ff49 100644 --- a/final/SRAM_bits.cir +++ b/final/SRAM_bits.cir @@ -179,8 +179,8 @@ Xh1 dot nn1 inv Xh2 nn1 dot inv .ends read1 -.subckt readSub btt bff set rst rwt clk -Xnd trigger rwt clk nnd2 +.subckt readSub btt bff set rst rwt clk en +Xnd trigger rwt clk en nnd3 Xinv triggerb trigger inv Xamp set rst btt bff triggerb senseAmp size='200' .ends read1 diff --git a/final/testBuffer.cir b/final/testBuffer.cir index 35c2dc7..b39a8ed 100644 --- a/final/testBuffer.cir +++ b/final/testBuffer.cir @@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5' *********begin: topLevel***** -.param per = 2ns +.param per = 3ns .param dataLead=per*0.1 .param lw=1800 .param wirew=12 @@ -31,7 +31,7 @@ vdd vdd 0 'supply' Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50 Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 Xdii din dat1 period='per' start='per' total=4 duty=2 sz=30 - +Xdec choose clk clk decModel Xwr bt1 bf1 din rdw clk write1 @@ -43,15 +43,14 @@ Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew' Xmd3 bt4 bf4 memLoad number=16 Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xmd4 btt bff memLoad number =15 -Xla btt bff clk mem1 -Xrd btt bff set rst rdw clk readSub +Xla btt bff choose mem1 +Xrd btt bff set rst rdw clk choose readSub Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect + .ic V(la:tt)=0 V(la:ff)=1 .ic V(bt2)=1 .tran 1p 'per*20' - - - +.meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1