From f317a7e8dae42062c6401897b2a9706608313342 Mon Sep 17 00:00:00 2001 From: Danila Fedorin Date: Wed, 17 Mar 2021 13:34:04 -0700 Subject: [PATCH] Add some minor additional sections to report. --- final/report.tex | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) diff --git a/final/report.tex b/final/report.tex index 6f2da37..b7663b7 100644 --- a/final/report.tex +++ b/final/report.tex @@ -359,6 +359,27 @@ space incurred, an entire column is approximately $100\lambda$ wide. \label{fig:layout-arrayed} \end{figure} +\pagebreak +\section{Further Design Ideas} +I discovered -- from other people in the class -- that an 8-column design was plausible. +Unfortunately, I was only convinced a day or so before the project was due, which did not give me +enough time to redesign my SRAM. I have seen students successfully using +the 8-column design by sharing \textsc{Wl} wires for each 'row', and using +the remaining 3 bits to enable and disable the write block. Since reading does +not change the cell value, this is a viable approach; all 8 columns would ``read'' +(except during writing, in which 7 columns would read and 1 would write). As +long as a proper address selection mechanism is implemented into the read collector +circuit (which at present cannot handle concurrent reads), this would work just +fine, albeit at the expense of added power consumption (from draining and re-charging +7 extra wires). This design, combined with my idea of placing the write block +in the middle of the column, can lead to very short effective wire lengths. If +I was to approach this project again, that's what I would try. + +\section{Acknowledgements} +Reed's aforementioned idea of sharing well contacts between adjacent cells +played a part in my design. Also, without the other students in the class +Discord, I would not have known to use the ``better'' wire model at all. + \pagebreak \bibliographystyle{unsrt} \bibliography{bibliography}