From f3ffb39219a74172814eb8c18e1c6caa75818185 Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Sun, 14 Mar 2021 23:11:00 -0700
Subject: [PATCH] Write-in-middle design.

---
 final/SRAM_bits.cir  | 24 ++++++++++++++++--------
 final/testBuffer.cir | 10 +++++-----
 final/todo.md        |  5 +++++
 3 files changed, 26 insertions(+), 13 deletions(-)
 create mode 100644 final/todo.md

diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir
index 557ff49..4a9f060 100644
--- a/final/SRAM_bits.cir
+++ b/final/SRAM_bits.cir
@@ -145,18 +145,26 @@ Xn0 ot0 in0 ot1 eva nnd3 size ='size'
 Xn1 ot1 in1 ot0 eva nnd3 size ='size'
 .ends senseAmp
 
+.subckt precharge charge rwtb clk diib
+Xrdi rdi rwtb diib nnd2
+Xnn chargeb clk rdi nnd2
+Xout charge chargeb inv
+.ends precharge
 
 .subckt write1 btt bff dii rwt clk
 * TODO: sizes
 Xclk clkb clk inv size='25'
 Xdii diib dii inv size='25'
+Xrwt rwtb rwt inv size='25'
 Xrwn dorw clkb rwt nor2 size='50'
-Xdt pdt dii gnd nn ww='50'
-Xdf pdf diib gnd nn ww='50'
-Xwt btt dorw pdt nn ww='50'
-Xwf bff dorw pdf nn ww='50'
-Xpct btt clk vdd pp ww='25'
-Xpcf bff clk vdd pp ww='25'
+Xdt pdt dii gnd nn  ww='30'
+Xdf pdf diib gnd nn ww='30'
+Xwt btt dorw pdt nn ww='30'
+Xwf bff dorw pdf nn ww='30'
+Xpcet pcet rwtb clk diib precharge
+Xpcef pcef rwtb clk dii precharge
+Xpct btt clk vdd pp ww='10'
+Xpcf bff clk vdd pp ww='10'
 .ends write1
 
 
@@ -181,8 +189,8 @@ Xh2 nn1 dot inv
 
 .subckt readSub btt bff set rst rwt clk en
 Xnd trigger rwt clk en nnd3
-Xinv triggerb trigger inv
-Xamp set rst btt bff triggerb senseAmp size='200'
+Xinv triggerb trigger inv size='40'
+Xamp set rst btt bff triggerb senseAmp size='40'
 .ends read1
 
 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3
diff --git a/final/testBuffer.cir b/final/testBuffer.cir
index b39a8ed..d5f9840 100644
--- a/final/testBuffer.cir
+++ b/final/testBuffer.cir
@@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
 
 
 *********begin: topLevel*****
-.param per = 3ns
+.param per = 1.15ns
 .param dataLead=per*0.1
 .param lw=1800
 .param wirew=12
@@ -34,16 +34,16 @@ Xdii din                dat1 period='per' start='per'          total=4 duty=2
 Xdec choose clk clk decModel
 
 
-Xwr bt1 bf1 din rdw clk write1
+Xwr bt3 bf3 din rdw clk write1
 Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
-Xmd1 bt2 bf2 memLoad number=16
+Xmd1 bt2 bf2 memLoad number=15
 Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'
 Xmd2 bt3 bf3 memLoad number=16
 Xw3 bt3 bt4 bf3 bf4  clk   wire_precharge len='lw/4' wid='wirew'
 Xmd3 bt4 bf4 memLoad number=16
 Xw4 bt4 btt bf4 bff  clk   wire_precharge len='lw/4' wid='wirew'
-Xmd4 btt bff             memLoad number =15
-Xla btt bff choose         mem1
+Xmd4 btt bff             memLoad number =16
+Xla bt1 bf1 clk         mem1
 Xrd btt bff set rst rdw clk choose readSub
 Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
 
diff --git a/final/todo.md b/final/todo.md
new file mode 100644
index 0000000..ff49f1c
--- /dev/null
+++ b/final/todo.md
@@ -0,0 +1,5 @@
+* [x] Figure out the weird opAmp behavior
+* [ ] Design cell with strict metal policies
+* [ ] Add precharger version of memory cell (or explain how they compose)
+* [ ] Test cell in the _middle_.
+* [ ] Walk through the consequences of the read/write block being in the middle.