From ff0edb93bbd6e4d50f33043fc0dc0964e0d0652f Mon Sep 17 00:00:00 2001
From: Danila Fedorin <danila.fedorin@gmail.com>
Date: Wed, 17 Mar 2021 12:58:36 -0700
Subject: [PATCH] Update with new wire model

---
 final/SRAM_bits.cir | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/final/SRAM_bits.cir b/final/SRAM_bits.cir
index c14bcae..cd4c47f 100644
--- a/final/SRAM_bits.cir
+++ b/final/SRAM_bits.cir
@@ -26,8 +26,8 @@
 
 
 .subckt wire iot iof len=10 wid=10
-.param rr=0.8
-.param cc = '200e-15'
+.param rr=0.4
+.param cc = '100e-15'
 rt iot iof 'rr*len*50/(wid)'
 cf iof  0  'cc*len*wid*50/1e6'
 
@@ -179,7 +179,7 @@ Xpct btt clk vdd pp ww='100'
 Xpcf bff clk vdd pp ww='100'
 .ends write1
 
-.subckt iWrite1 btt bff dii rwt clk
+.subckt iWrite1 btt bff dii rwt en clk
 * TODO: sizes
 Xclk clkb clk inv size='40'
 Xdii diib dii inv size='40'
@@ -222,7 +222,7 @@ Xamp set rst btt bff triggerb senseAmp size='200'
 .subckt iReadSub btt bff set rst rwt clk en
 Xnd trigger rwt en clk nnd3
 Xinv triggerb trigger inv size='40'
-Xamp set rst btt bff triggerb iSenseAmp size='40'
+Xamp set rst btt bff triggerb iSenseAmp size='120'
 .ends read1
 
 .subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3