*Assignment:
* Find the measured logical effort for a two input NOR gate, and a two input NAND gate
* empirically by taking the ratio of slopes for delay vs fanout for the logic gates
* and an inverter.
* Plot delay as a function of fanout for an inverter, 2 input Nor and Nand.
* measure the slopes of these lines.
* ratio the slopes for Nand  and Nor to that of the inverter
* how does that compare to back of envelope calculation for this technology?


***** long channel VTP = -0.9, VTN = 0.8 *****
* .include modelcard/1um.pm
* .param supply = 5
* .param ll = 1u

****** 50nm models***
* .include ./modelcard/50nm.pm
* .param supply =1
* .param ll=50nm


****** 16nm low power models***
* .include ./modelcard/PTM_LP/16nm.pm
* .param supply =0.9
* .param ll=16nm

****** 16nm high peformance models***
.include ./modelcard/PTM_HP/16nm.pm
.param supply =0.7
.param ll=16nm






.subckt nn d g s  ww=100nm
mnfet d g s 0 nmos L=ll w=ww
.ends

.subckt pp d g s   ww=100nm
mpfet d g s vdd pmos L=ll w=ww
.ends


.subckt inv out inn size=100n beta=2
XPP out inn vdd pp ww='size*beta/(beta+1)'
XNN out inn 0   nn ww='size/(beta+1)'
.ENDS inv

.subckt nd2 out in0 in1 size=100n beta=2
Xp0 out in0 vdd pp ww='beta*size/(beta+2)'
Xp1 out in1 vdd pp ww='beta*size/(beta+2)'
Xn0 out in0 nnn nn ww='2*size/(beta+2)'
Xn1 nnn in1 gnd nn ww='2*size/(beta+2)'
.ends nd2

.subckt no2 out in0 in1 size=100n beta=2
Xp0 nnn in0 vdd pp ww='2*beta*size/(2*beta+1)'
Xp1 out in1 nnn pp ww='2*beta*size/(2*beta+1)'
Xn0 out in0 gnd nn ww='size/(2*beta+1)'
Xn1 out in1 gnd nn ww='size/(2*beta+1)'
.ends no2

.subckt dut out inn size = 10 bb = 1.5
* xdut out inn inv size='size' beta='bb'
* Xnn2 out inn vdd nd2 size='size' beta='bb'
* Xno2 out inn gnd no2 size='size' beta='bb'
Xno2 out gnd inn no2 size='size' beta='bb'
.ends  dut

*********begin: topLevel*****
.ic v(n0)=0
.param mm=1
.param gg=100
x0 n1 n0 dut  size='gg*ll'
x1 n2 n1 dut  size='gg*ll'
x2 n3 n2 dut  size='gg*ll'
x3 n4 n3 dut  size='gg*ll'
x4 n5 n4 dut  size='gg*ll'
x5 n6 n5 dut  size='gg*ll'
x6 n0 n6 dut  size='gg*ll'

x7 thr thr dut size='gg*ll'

xl0 p1 n0 dut size={ll*gg*mm}
xl1 p2 n1 dut size={ll*gg*mm}
xl2 p3 n2 dut size={ll*gg*mm}
xl3 p4 n3 dut size={ll*gg*mm}
xl4 p5 n4 dut size={ll*gg*mm}
xl5 p6 n5 dut size={ll*gg*mm}
xl6 p0 n6 dut size={ll*gg*mm}


* Parameters
.global gnd vdd
.param gnd=0


*DC supplies
vdd vdd 0 'supply'

* this line directs the simulator to perform a transient analysis
* .tran <timestep> <simulationLength>
.tran 1p 40n




* Below are  measurment statements that direct the simulator to make the specified measurements and write the to *.log file
* Search the *.log file for the names (ivdd, del10,del1, rtime, ftime) to find the results.
* one can also measure these value in the waveform viewer
.meas ivdd find i(vdd) at=1.8n
.meas thresh find v(thr) at=1.8n
.meas del10 trig v(n1) val='0.5*supply'   cross =2 targ v(n1) val='0.5*supply'   cross =12
.meas del1 param = 'del10/70'
.meas rtime  trig v(n2) val= '0.1 * supply' rise = 2 targ v(n2) val = '0.9*supply' rise =2
.meas ftime  trig v(n2) val= '0.9 * supply' fall = 2 targ v(n2) val = '0.1*supply' fall =2