472 lines
13 KiB
C
472 lines
13 KiB
C
/*******************************************************************************
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*
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* Copyright (c) 2018 Dragino
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*
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* http://www.dragino.com
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*
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*******************************************************************************/
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#include <string>
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#include <stdio.h>
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#include <sys/types.h>
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#include <sys/socket.h>
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#include <arpa/inet.h>
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#include <string.h>
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#include <sys/time.h>
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#include <signal.h>
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#include <stdlib.h>
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#include <sys/ioctl.h>
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#include <wiringPi.h>
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#include <wiringPiSPI.h>
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// #############################################
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// #############################################
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#define REG_FIFO 0x00
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#define REG_OPMODE 0x01
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#define REG_FIFO_ADDR_PTR 0x0D
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#define REG_FIFO_TX_BASE_AD 0x0E
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#define REG_FIFO_RX_BASE_AD 0x0F
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#define REG_RX_NB_BYTES 0x13
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_IRQ_FLAGS 0x12
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#define REG_DIO_MAPPING_1 0x40
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#define REG_DIO_MAPPING_2 0x41
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#define REG_MODEM_CONFIG 0x1D
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#define REG_MODEM_CONFIG2 0x1E
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#define REG_MODEM_CONFIG3 0x26
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#define REG_SYMB_TIMEOUT_LSB 0x1F
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#define REG_PKT_SNR_VALUE 0x19
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_IRQ_FLAGS_MASK 0x11
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#define REG_MAX_PAYLOAD_LENGTH 0x23
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#define REG_HOP_PERIOD 0x24
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#define REG_SYNC_WORD 0x39
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#define REG_VERSION 0x42
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#define PAYLOAD_LENGTH 0x40
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// LOW NOISE AMPLIFIER
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#define REG_LNA 0x0C
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#define LNA_MAX_GAIN 0x23
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#define LNA_OFF_GAIN 0x00
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#define LNA_LOW_GAIN 0x20
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#define RegDioMapping1 0x40 // common
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#define RegDioMapping2 0x41 // common
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#define RegPaConfig 0x09 // common
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#define RegPaRamp 0x0A // common
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#define RegPaDac 0x5A // common
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#define SX72_MC2_FSK 0x00
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#define SX72_MC2_SF7 0x70
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#define SX72_MC2_SF8 0x80
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#define SX72_MC2_SF9 0x90
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#define SX72_MC2_SF10 0xA0
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#define SX72_MC2_SF11 0xB0
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#define SX72_MC2_SF12 0xC0
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#define SX72_MC1_LOW_DATA_RATE_OPTIMIZE 0x01 // mandated for SF11 and SF12
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// sx1276 RegModemConfig1
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#define SX1276_MC1_BW_125 0x70
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#define SX1276_MC1_BW_250 0x80
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#define SX1276_MC1_BW_500 0x90
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#define SX1276_MC1_CR_4_5 0x02
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#define SX1276_MC1_CR_4_6 0x04
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#define SX1276_MC1_CR_4_7 0x06
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#define SX1276_MC1_CR_4_8 0x08
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#define SX1276_MC1_IMPLICIT_HEADER_MODE_ON 0x01
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// sx1276 RegModemConfig2
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#define SX1276_MC2_RX_PAYLOAD_CRCON 0x04
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// sx1276 RegModemConfig3
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#define SX1276_MC3_LOW_DATA_RATE_OPTIMIZE 0x08
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#define SX1276_MC3_AGCAUTO 0x04
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// preamble for lora networks (nibbles swapped)
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#define LORA_MAC_PREAMBLE 0x34
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#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG1 0x0A
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#ifdef LMIC_SX1276
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#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x70
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#elif LMIC_SX1272
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#define RXLORA_RXMODE_RSSI_REG_MODEM_CONFIG2 0x74
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#endif
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// FRF
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define FRF_MSB 0xD9 // 868.1 Mhz
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#define FRF_MID 0x06
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#define FRF_LSB 0x66
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// ----------------------------------------
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// Constants for radio registers
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#define OPMODE_LORA 0x80
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#define OPMODE_MASK 0x07
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#define OPMODE_SLEEP 0x00
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#define OPMODE_STANDBY 0x01
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#define OPMODE_FSTX 0x02
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#define OPMODE_TX 0x03
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#define OPMODE_FSRX 0x04
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#define OPMODE_RX 0x05
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#define OPMODE_RX_SINGLE 0x06
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#define OPMODE_CAD 0x07
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// ----------------------------------------
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// Bits masking the corresponding IRQs from the radio
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#define IRQ_LORA_RXTOUT_MASK 0x80
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#define IRQ_LORA_RXDONE_MASK 0x40
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#define IRQ_LORA_CRCERR_MASK 0x20
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#define IRQ_LORA_HEADER_MASK 0x10
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#define IRQ_LORA_TXDONE_MASK 0x08
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#define IRQ_LORA_CDDONE_MASK 0x04
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#define IRQ_LORA_FHSSCH_MASK 0x02
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#define IRQ_LORA_CDDETD_MASK 0x01
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// DIO function mappings D0D1D2D3
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#define MAP_DIO0_LORA_RXDONE 0x00 // 00------
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#define MAP_DIO0_LORA_TXDONE 0x40 // 01------
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#define MAP_DIO1_LORA_RXTOUT 0x00 // --00----
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#define MAP_DIO1_LORA_NOP 0x30 // --11----
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#define MAP_DIO2_LORA_NOP 0xC0 // ----11--
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// #############################################
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// #############################################
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//
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typedef bool boolean;
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typedef unsigned char byte;
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static const int CHANNEL = 0;
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char message[256];
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const char tok[2] = "|";
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bool sx1272 = true;
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byte receivedbytes;
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enum sf_t { SF7=7, SF8, SF9, SF10, SF11, SF12 };
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/*******************************************************************************
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*
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* Configure these values!
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*
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*******************************************************************************/
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// SX1272 - Raspberry connections
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int ssPin = 6;
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int dio0 = 7;
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int RST = 0;
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// Set spreading factor (SF7 - SF12)
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sf_t sf = SF7;
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// Set center frequency
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uint32_t freq = 915000000; // in Mhz! (868.1)
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byte hello[32] = "HELLO";
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void txlora(byte *frame, byte datalen);
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static void configPower (int8_t pw);
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void die(const char *s)
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{
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perror(s);
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exit(1);
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}
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void selectreceiver()
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{
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digitalWrite(ssPin, LOW);
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}
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void unselectreceiver()
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{
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digitalWrite(ssPin, HIGH);
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}
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byte readReg(byte addr)
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{
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unsigned char spibuf[2];
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selectreceiver();
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spibuf[0] = addr & 0x7F;
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spibuf[1] = 0x00;
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wiringPiSPIDataRW(CHANNEL, spibuf, 2);
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unselectreceiver();
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return spibuf[1];
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}
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void writeReg(byte addr, byte value)
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{
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unsigned char spibuf[2];
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spibuf[0] = addr | 0x80;
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spibuf[1] = value;
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selectreceiver();
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wiringPiSPIDataRW(CHANNEL, spibuf, 2);
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unselectreceiver();
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}
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static void opmode (uint8_t mode) {
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writeReg(REG_OPMODE, (readReg(REG_OPMODE) & ~OPMODE_MASK) | mode);
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}
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static void opmodeLora() {
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uint8_t u = OPMODE_LORA;
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if (sx1272 == false)
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u |= 0x8; // TBD: sx1276 high freq
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writeReg(REG_OPMODE, u);
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}
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void SetupLoRa()
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{
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digitalWrite(RST, HIGH);
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delay(100);
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digitalWrite(RST, LOW);
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delay(100);
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byte version = readReg(REG_VERSION);
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if (version == 0x22) {
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// sx1272
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printf("SX1272 detected, starting.\n");
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sx1272 = true;
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} else {
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// sx1276?
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digitalWrite(RST, LOW);
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delay(100);
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digitalWrite(RST, HIGH);
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delay(100);
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version = readReg(REG_VERSION);
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if (version == 0x12) {
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// sx1276
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//printf("SX1276 detected, starting.\n");
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sx1272 = false;
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} else {
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printf("Unrecognized transceiver.\n");
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//printf("Version: 0x%x\n",version);
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exit(1);
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}
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}
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opmode(OPMODE_SLEEP);
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// set frequency
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uint64_t frf = ((uint64_t)freq << 19) / 32000000;
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writeReg(REG_FRF_MSB, (uint8_t)(frf>>16) );
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writeReg(REG_FRF_MID, (uint8_t)(frf>> 8) );
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writeReg(REG_FRF_LSB, (uint8_t)(frf>> 0) );
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writeReg(REG_SYNC_WORD, 0x34); // LoRaWAN public sync word
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if (sx1272) {
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if (sf == SF11 || sf == SF12) {
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writeReg(REG_MODEM_CONFIG,0x0B);
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} else {
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writeReg(REG_MODEM_CONFIG,0x0A);
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}
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writeReg(REG_MODEM_CONFIG2,(sf<<4) | 0x04);
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} else {
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if (sf == SF11 || sf == SF12) {
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writeReg(REG_MODEM_CONFIG3,0x0C);
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} else {
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writeReg(REG_MODEM_CONFIG3,0x04);
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}
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writeReg(REG_MODEM_CONFIG,0x72);
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writeReg(REG_MODEM_CONFIG2,(sf<<4) | 0x04);
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}
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if (sf == SF10 || sf == SF11 || sf == SF12) {
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writeReg(REG_SYMB_TIMEOUT_LSB,0x05);
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} else {
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writeReg(REG_SYMB_TIMEOUT_LSB,0x08);
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}
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writeReg(REG_MAX_PAYLOAD_LENGTH,0x80);
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writeReg(REG_PAYLOAD_LENGTH,PAYLOAD_LENGTH);
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writeReg(REG_HOP_PERIOD,0xFF);
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writeReg(REG_FIFO_ADDR_PTR, readReg(REG_FIFO_RX_BASE_AD));
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writeReg(REG_LNA, LNA_MAX_GAIN);
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}
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boolean receive(char *payload) {
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// clear rxDone
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writeReg(REG_IRQ_FLAGS, 0x40);
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int irqflags = readReg(REG_IRQ_FLAGS);
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// payload crc: 0x20
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if((irqflags & 0x20) == 0x20)
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{
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printf("CRC error\n");
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writeReg(REG_IRQ_FLAGS, 0x20);
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return false;
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} else {
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byte currentAddr = readReg(REG_FIFO_RX_CURRENT_ADDR);
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byte receivedCount = readReg(REG_RX_NB_BYTES);
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receivedbytes = receivedCount;
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writeReg(REG_FIFO_ADDR_PTR, currentAddr);
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for(int i = 0; i < receivedCount; i++)
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{
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payload[i] = (char)readReg(REG_FIFO);
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}
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}
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return true;
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}
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int send(char * s) {
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opmode(OPMODE_STANDBY);
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txlora((byte *) s, strlen((char *) s));
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SetupLoRa();
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opmodeLora();
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opmode(OPMODE_STANDBY);
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writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08);
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configPower(23);
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opmode(OPMODE_RX);
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return 1;
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}
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void receivepacket() {
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long int SNR;
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int rssicorr;
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if(digitalRead(dio0) == 1)
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{
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if(receive(message)) {
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byte value = readReg(REG_PKT_SNR_VALUE);
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if( value & 0x80 ) // The SNR sign bit is 1
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{
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// Invert and divide by 4
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value = ( ( ~value + 1 ) & 0xFF ) >> 2;
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SNR = -value;
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}
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else
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{
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// Divide by 4
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SNR = ( value & 0xFF ) >> 2;
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}
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if (sx1272) {
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rssicorr = 139;
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} else {
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rssicorr = 157;
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}
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/*
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printf("Packet RSSI: %d, ", readReg(0x1A)-rssicorr);
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printf("RSSI: %d, ", readReg(0x1B)-rssicorr);
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printf("SNR: %li, ", SNR);
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printf("Length: %i", (int)receivedbytes);
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printf("\n");
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printf("Payload: %s\n", message);
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*/
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printf("Received message: %s", message);
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} // received a message
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} // dio0=1
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}
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static void configPower (int8_t pw) {
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if (sx1272 == false) {
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// no boost used for now
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if(pw >= 17) {
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pw = 15;
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} else if(pw < 2) {
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pw = 2;
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}
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// check board type for BOOST pin
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writeReg(RegPaConfig, (uint8_t)(0x80|(pw&0xf)));
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writeReg(RegPaDac, readReg(RegPaDac)|0x4);
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} else {
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// set PA config (2-17 dBm using PA_BOOST)
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if(pw > 17) {
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pw = 17;
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} else if(pw < 2) {
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pw = 2;
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}
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writeReg(RegPaConfig, (uint8_t)(0x80|(pw-2)));
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}
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}
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static void writeBuf(byte addr, byte *value, byte len) {
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unsigned char spibuf[256];
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spibuf[0] = addr | 0x80;
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for (int i = 0; i < len; i++) {
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spibuf[i + 1] = value[i];
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}
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selectreceiver();
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wiringPiSPIDataRW(CHANNEL, spibuf, len + 1);
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unselectreceiver();
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}
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void txlora(byte *frame, byte datalen) {
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// set the IRQ mapping DIO0=TxDone DIO1=NOP DIO2=NOP
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writeReg(RegDioMapping1, MAP_DIO0_LORA_TXDONE|MAP_DIO1_LORA_NOP|MAP_DIO2_LORA_NOP);
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// clear all radio IRQ flags
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writeReg(REG_IRQ_FLAGS, 0xFF);
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// mask all IRQs but TxDone
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writeReg(REG_IRQ_FLAGS_MASK, ~IRQ_LORA_TXDONE_MASK);
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// initialize the payload size and address pointers
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writeReg(REG_FIFO_TX_BASE_AD, 0x00);
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writeReg(REG_FIFO_ADDR_PTR, 0x00);
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writeReg(REG_PAYLOAD_LENGTH, datalen);
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// download buffer to the radio FIFO
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writeBuf(REG_FIFO, frame, datalen);
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// now we actually start the transmission
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opmode(OPMODE_TX);
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printf("send: %s\n", frame);
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}
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int main (int argc, char *argv[]) {
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wiringPiSetup () ;
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pinMode(ssPin, OUTPUT);
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pinMode(dio0, INPUT);
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pinMode(RST, OUTPUT);
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wiringPiSPISetup(CHANNEL, 500000);
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SetupLoRa();
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opmodeLora();
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opmode(OPMODE_STANDBY);
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writeReg(RegPaRamp, (readReg(RegPaRamp) & 0xF0) | 0x08);
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configPower(23);
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opmode(OPMODE_RX);
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while(1) {
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receivepacket();
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delay(1);
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}
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return (0);
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}
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