Labs/Lab3/lab3.tex

\documentclass{article}
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\begin{document}
\section*{Lab 2}
\newcommand{\width}{0.6\linewidth}

The following five tables present the collected data for
the 4 technologies, as well as an additional measurement
of the high-power $16nm$ technology with $\beta=1.5$.
The first three columns are in seconds, while the last
column is the normalized logical effort. The first
row ($h=0$) is extrapolated from the other two data points.

\begin{figure}[h]
    \centering
    \begin{tabular}{lccccc}
         & Inverter & NAND & NOR (1) & NOR (2)  \\
        \hline
        $h=0$ & 1.70E-11 & 2.37E-11 & 9.52E-11 & 2.69E-11 \\
        $h=2$ & 1.74E-10 & 2.00E-10 & 2.98E-10 & 2.50E-10 \\
        $h=4$ & 3.31E-10 & 3.76E-10 & 5.00E-10 & 4.74E-10 \\
        $\frac{dt}{dh}$ & 7.85E-11 & 8.81E-11 & 1.01E-10 & 1.12E-10 \\
        $g$ & 1.00E+00 & 1.12E+00 & 1.29E+00 & 1.42E+00 
    \end{tabular}
    \label{fig:1um}
    \caption{Delays, Slopes, and Logical Efforts of Gates at $1\mu m$}
\end{figure}

\begin{figure}[h]
    \centering
    \begin{tabular}{lccccc}
         & Inverter & NAND & NOR (1) & NOR (2)  \\
        \hline
        $h=0$ & 7.50E-12 & 1.39E-11 & 2.96E-11 & 1.42E-11 \\
        $h=2$ & 3.57E-11 & 4.83E-11 & 6.73E-11 & 5.89E-11 \\
        $h=4$ & 6.40E-11 & 8.27E-11 & 1.05E-10 & 1.04E-10 \\
        $\frac{dt}{dh}$ & 1.41E-11 & 1.72E-11 & 1.89E-11 & 2.23E-11 \\
        $g$ & 1.00E+00 & 1.22E+00 & 1.34E+00 & 1.58E+00
    \end{tabular}
    \label{fig:50nm}
    \caption{Delays, Slopes, and Logical Efforts of Gates at $50nm$}
\end{figure}

\begin{figure}[h]
    \centering
    \begin{tabular}{lccccc}
         & Inverter & NAND & NOR (1) & NOR (2)  \\
         \hline
        $h=0$ & 6.12E-12 & 1.21E-11 & 2.32E-11 & 1.52E-11 \\
        $h=2$ & 2.30E-11 & 3.48E-11 & 5.50E-11 & 4.80E-11 \\
        $h=4$ & 3.99E-11 & 5.75E-11 & 8.69E-11 & 8.07E-11 \\
        $\frac{dt}{dh}$ & 8.44E-12 & 1.13E-11 & 1.59E-11 & 1.64E-11 \\
        $g$ & 1.00E+00 & 1.34E+00 & 1.89E+00 & 1.94E+00 \\
    \end{tabular}
    \label{fig:16nmlp}
    \caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (LP)}
\end{figure}

\begin{figure}[h!]
    \centering
    \begin{tabular}{lccccc}
         & Inverter & NAND & NOR (1) & NOR (2)  \\
         \hline
        $h=0$ & 1.87E-12 & 4.21E-12 & 7.84E-12 & 3.71E-12 \\
        $h=2$ & 5.14E-12 & 8.11E-12 & 1.26E-11 & 9.58E-12 \\
        $h=4$ & 8.41E-12 & 1.20E-11 & 1.73E-11 & 1.54E-11 \\
        $\frac{dt}{dh}$ & 1.63E-12 & 1.95E-12 & 2.37E-12 & 2.93E-12 \\
        $g$ & 1.00E+00 & 1.19E+00 & 1.45E+00 & 1.80E+00 \\
    \end{tabular}
    \label{fig:16nmhp}
    \caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (HP)}
\end{figure}

\begin{figure}[h!]
    \centering
    \begin{tabular}{lccccc}
         & Inverter & NAND & NOR (1) & NOR (2)  \\
         \hline
        $h=0$ & 1.87E-12 & 3.88E-12 & 7.12E-12 & 3.57E-12 \\
        $h=2$ & 4.99E-12 & 7.90E-12 & 1.17E-11 & 9.09E-12 \\
        $h=4$ & 8.11E-12 & 1.19E-11 & 1.62E-11 & 1.46E-11 \\
        $\frac{dt}{dh}$ & 1.56E-12 & 2.01E-12 & 2.27E-12 & 2.76E-12 \\
        $g$ & 1.00E+00 & 1.29E+00 & 1.45E+00 & 1.77E+00 \\
    \end{tabular}
    \label{fig:16nmhpbeta}
    \caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (HP) and $\beta=1.5$}
\end{figure}

\pagebreak

\begin{multicols}{2}
    \includegraphics[width=\linewidth]{1um.png} \par
    \includegraphics[width=\linewidth]{50nm.png} \par
\end{multicols}
\begin{multicols}{2}
    \includegraphics[width=\linewidth]{16nmlp.png} \par
    \includegraphics[width=\linewidth]{16nmhp.png} \par
\end{multicols}

\begin{figure}[h!]
    \centering
    \includegraphics[width=0.5\linewidth]{16nmhpbeta.png}
\end{figure}

I'm not completely certain why different technologies
would have differing logical efforts. However, I would
assume that in the case of smaller technologies, the issue
is due to various short-channel effects. For intance,
if the transistors are ``leaky'', and we're trying
to pull the output up, some of the charge will
consistently escape through the nMOS transistors,
increasing the time it would take to charge the
output capacitor. This effect would scale with the electrical
effort, since it would affectively lower the rate at which
charge flows into the output. The lab data is consistent
with this prediction, with normalized logical effort
values being consistently higher in smaller technologies.
Furthermore, with effects such as DIBL, it's possible
that the CMOS assembly spends more time with both
the nMOS and pMOS transistors conducting current,
which again would reduce the rate at which we
can charge the output.

The linear analysis that we typically perform rests on many
levels of simplification. One of these levels ignores all but
the capacitance of the transistors connected to the output
to estimate a gate's output capacitance. However, depending
on the situation, the capacitances of other transistors
can play a role in the final output as well. This is
the case for a NOR gate, specifically when it's being pulled
down. It's possible that the ``top'' nMOS transistor of this
gate was transparent while its output was high, which
would charge the inner diffusion node between the two nMOs transistors
to roughly $V_{GT}$. This contributes additional
charge to the output, so it takes longer to pull down.

In our specific situation, one input is constantly connected
to $V_{dd}$, meaning that it is transparent. If this is
the top input, it would allow charge into the shared nMOS
diffusion region, causing a delay as described above.
This is precisely what we see in the data: the NOR(1)
column, in which the ``top`` transistor is connected
to $V_dd$, the delays are higher.

I used an alternative value of $\beta=1.5$. For the NAND gate, the logical effort
increased (from 1.19 to 1.29). I believe
that this is due to the resistances of the the pMOS transistors
(which are affected by this change). In the NAND gate, there are
two pMOS transistors in parallel. When beta is reduced from 2 to 1.5,
their resistance goes up by a factor of $4/3$. Since the pull up time of the NAND
gate is affected by the resistance of these transistors, and since this
resistance now increased, it takes longer to pull up, leading to larger
gate effort. This is further accentuated by the fact that one of the NAND
inputs is tied to $V_{dd}$, which means the output is always pulled up
via a single, higher-resistance transistor. 

\end{document}