2021-03-14 23:11:00 -07:00
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* [x] Figure out the weird opAmp behavior
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* [ ] Design cell with strict metal policies
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* [ ] Add precharger version of memory cell (or explain how they compose)
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* [ ] Test cell in the _middle_.
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* [ ] Walk through the consequences of the read/write block being in the middle.
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2021-03-16 18:19:45 -07:00
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* [ ] Test data close to write block (it pulls up past clock low!)
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* [ ] Drive wires to zero?
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