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Add TODO.

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This commit is contained in:
Danila Fedorin 2021-03-17 11:51:50 -07:00
parent 6f99879b8f
commit 9afa839bff
2 changed files with 9 additions and 9 deletions
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10
final/testBuffer.cir
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@ -21,17 +21,17 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel*****
.param per = 1.33ns
.param per = 1.34ns
.param dataLead=per*0.1
.param lw=2000
.param lw=2200
.param wirew=14
vdd vdd 0 'supply'
Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300
Xrdwr rdw dat1 period='3*per' start='2*per' total=2 duty=1 sz=300
Xdii din dat1 period='3*per' start='per' total=4 duty=2 sz=300
Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=300
Xdii din dat1 period='per' start='per' total=4 duty=2 sz=300
Xinv1 clkb1 clk inv
Xinv2 clkb2 clkb1 inv
@ -54,7 +54,7 @@ Xmd2 bt3 bf3 memLoad number=16
Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 btt bff memLoad number =16
Xmd4 bt3 bf3 memLoad number =16
Xla bt1 bf1 choose mem1
Xrd btt bff set rst rdwf clk choose iReadSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect

8
final/todo.md
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@ -6,8 +6,8 @@
* [x] Figure out what to do with flopped write block.
* [x] Test data close to write block (it pulls up past clock low!)
* [ ] Drive wires to zero?
* [ ] Add missing well connection in layout
* [ ] Make sure width isn't too horrible
* [x] Add missing well connection in layout
* [x] Make sure width isn't too horrible
* [ ] Model additional delay for read read/write block select?
* [ ] Model worst case of decoder
* [ ] Cite [this](https://ieeexplore.ieee.org/document/210039)
* [x] Model worst case of decoder
* [x] Cite [this](https://ieeexplore.ieee.org/document/210039)