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1.35ns with flip flops and bug mitigation

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This commit is contained in:
Danila Fedorin 2021-03-16 16:20:35 -07:00
parent 76899cb8a3
commit e077bb9071
2 changed files with 10 additions and 10 deletions
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8
final/SRAM_bits.cir
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@ -185,10 +185,10 @@ Xclk clkb clk inv size='40'
Xdii diib dii inv size='40' Xdii diib dii inv size='40'
Xrwt rwtb rwt inv size='40' Xrwt rwtb rwt inv size='40'
Xrwn dorw clkb rwt nor2 size='110' Xrwn dorw clkb rwt nor2 size='110'
Xdt pdt dii gnd nn ww='300' Xdt pdt dii gnd nn ww='200'
Xdf pdf diib gnd nn ww='300' Xdf pdf diib gnd nn ww='200'
Xwt btt dorw pdt nn ww='300' Xwt btt dorw pdt nn ww='200'
Xwf bff dorw pdf nn ww='300' Xwf bff dorw pdf nn ww='200'
Xpcet pcet rwtb clk diib precharge Xpcet pcet rwtb clk diib precharge
Xpcef pcef rwtb clk dii precharge Xpcef pcef rwtb clk dii precharge
Xpct btt pcet vdd pp ww='100' Xpct btt pcet vdd pp ww='100'

12
final/testBuffer.cir
View File

@ -21,24 +21,24 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel***** *********begin: topLevel*****
.param per = 2ns .param per = 1.35ns
.param dataLead=per*0.1 .param dataLead=per*0.1
.param lw=2000 .param lw=2000
.param wirew=12 .param wirew=14
vdd vdd 0 'supply' vdd vdd 0 'supply'
Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300 Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300 Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300
Xrdwr rdw dat1 period='2*per' start='2*per' total=2 duty=1 sz=300 Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=300
Xdii din dat1 period='2*per' start='per' total=4 duty=2 sz=300 Xdii din dat1 period='per' start='per' total=4 duty=2 sz=300
Xinv1 clkb1 clk inv Xinv1 clkb1 clk inv
Xinv2 clkb2 clkb1 inv Xinv2 clkb2 clkb1 inv
Xinv3 clkb3 clkb2 inv Xinv3 clkb3 clkb2 inv
Xinv4 clkb4 clkb3 inv Xinv4 clkb4 clkb3 inv size='300'
Xinv5 clkb5 clkb4 inv Xinv5 clkb5 clkb4 inv
Xinv6 clkb6 clkb5 inv size='500' Xinv6 clkb6 clkb5 inv size='300'
Xad adf ad clk flop Xad adf ad clk flop
Xdinff dinf din clk flop Xdinff dinf din clk flop