162 lines
6.4 KiB
TeX
162 lines
6.4 KiB
TeX
\documentclass{article}
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\usepackage[margin=1in]{geometry}
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\usepackage{amsmath}
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\usepackage{graphicx}
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\usepackage{multicol}
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\begin{document}
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\section*{Lab 2}
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\newcommand{\width}{0.6\linewidth}
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The following five tables present the collected data for
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the 4 technologies, as well as an additional measurement
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of the high-power $16nm$ technology with $\beta=1.5$.
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The first three columns are in seconds, while the last
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column is the normalized logical effort. The first
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row ($h=0$) is extrapolated from the other two data points.
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\begin{figure}[h]
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\centering
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\begin{tabular}{lccccc}
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& Inverter & NAND & NOR (1) & NOR (2) \\
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\hline
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$h=0$ & 1.70E-11 & 2.37E-11 & 9.52E-11 & 2.69E-11 \\
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$h=2$ & 1.74E-10 & 2.00E-10 & 2.98E-10 & 2.50E-10 \\
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$h=4$ & 3.31E-10 & 3.76E-10 & 5.00E-10 & 4.74E-10 \\
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$\frac{dt}{dh}$ & 7.85E-11 & 8.81E-11 & 1.01E-10 & 1.12E-10 \\
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$g$ & 1.00E+00 & 1.12E+00 & 1.29E+00 & 1.42E+00
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\end{tabular}
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\label{fig:1um}
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\caption{Delays, Slopes, and Logical Efforts of Gates at $1\mu m$}
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\end{figure}
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\begin{figure}[h]
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\centering
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\begin{tabular}{lccccc}
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& Inverter & NAND & NOR (1) & NOR (2) \\
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\hline
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$h=0$ & 7.50E-12 & 1.39E-11 & 2.96E-11 & 1.42E-11 \\
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$h=2$ & 3.57E-11 & 4.83E-11 & 6.73E-11 & 5.89E-11 \\
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$h=4$ & 6.40E-11 & 8.27E-11 & 1.05E-10 & 1.04E-10 \\
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$\frac{dt}{dh}$ & 1.41E-11 & 1.72E-11 & 1.89E-11 & 2.23E-11 \\
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$g$ & 1.00E+00 & 1.22E+00 & 1.34E+00 & 1.58E+00
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\end{tabular}
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\label{fig:50nm}
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\caption{Delays, Slopes, and Logical Efforts of Gates at $50nm$}
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\end{figure}
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\begin{figure}[h]
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\centering
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\begin{tabular}{lccccc}
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& Inverter & NAND & NOR (1) & NOR (2) \\
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\hline
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$h=0$ & 6.12E-12 & 1.21E-11 & 2.32E-11 & 1.52E-11 \\
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$h=2$ & 2.30E-11 & 3.48E-11 & 5.50E-11 & 4.80E-11 \\
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$h=4$ & 3.99E-11 & 5.75E-11 & 8.69E-11 & 8.07E-11 \\
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$\frac{dt}{dh}$ & 8.44E-12 & 1.13E-11 & 1.59E-11 & 1.64E-11 \\
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$g$ & 1.00E+00 & 1.34E+00 & 1.89E+00 & 1.94E+00 \\
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\end{tabular}
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\label{fig:16nmlp}
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\caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (LP)}
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\end{figure}
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\begin{figure}[h!]
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\centering
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\begin{tabular}{lccccc}
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& Inverter & NAND & NOR (1) & NOR (2) \\
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\hline
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$h=0$ & 1.87E-12 & 4.21E-12 & 7.84E-12 & 3.71E-12 \\
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$h=2$ & 5.14E-12 & 8.11E-12 & 1.26E-11 & 9.58E-12 \\
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$h=4$ & 8.41E-12 & 1.20E-11 & 1.73E-11 & 1.54E-11 \\
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$\frac{dt}{dh}$ & 1.63E-12 & 1.95E-12 & 2.37E-12 & 2.93E-12 \\
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$g$ & 1.00E+00 & 1.19E+00 & 1.45E+00 & 1.80E+00 \\
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\end{tabular}
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\label{fig:16nmhp}
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\caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (HP)}
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\end{figure}
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\begin{figure}[h!]
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\centering
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\begin{tabular}{lccccc}
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& Inverter & NAND & NOR (1) & NOR (2) \\
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\hline
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$h=0$ & 1.87E-12 & 3.88E-12 & 7.12E-12 & 3.57E-12 \\
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$h=2$ & 4.99E-12 & 7.90E-12 & 1.17E-11 & 9.09E-12 \\
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$h=4$ & 8.11E-12 & 1.19E-11 & 1.62E-11 & 1.46E-11 \\
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$\frac{dt}{dh}$ & 1.56E-12 & 2.01E-12 & 2.27E-12 & 2.76E-12 \\
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$g$ & 1.00E+00 & 1.29E+00 & 1.45E+00 & 1.77E+00 \\
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\end{tabular}
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\label{fig:16nmhpbeta}
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\caption{Delays, Slopes, and Logical Efforts of Gates at $16nm$ (HP) and $\beta=1.5$}
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\end{figure}
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\pagebreak
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\begin{multicols}{2}
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\includegraphics[width=\linewidth]{1um.png} \par
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\includegraphics[width=\linewidth]{50nm.png} \par
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\end{multicols}
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\begin{multicols}{2}
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\includegraphics[width=\linewidth]{16nmlp.png} \par
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\includegraphics[width=\linewidth]{16nmhp.png} \par
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\end{multicols}
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\begin{figure}[h!]
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\centering
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\includegraphics[width=0.5\linewidth]{16nmhpbeta.png}
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\end{figure}
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I'm not completely certain why different technologies
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would have differing logical efforts. However, I would
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assume that in the case of smaller technologies, the issue
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is due to various short-channel effects. For intance,
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if the transistors are ``leaky'', and we're trying
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to pull the output up, some of the charge will
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consistently escape through the nMOS transistors,
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increasing the time it would take to charge the
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output capacitor. This effect would scale with the electrical
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effort, since it would affectively lower the rate at which
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charge flows into the output. The lab data is consistent
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with this prediction, with normalized logical effort
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values being consistently higher in smaller technologies.
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Furthermore, with effects such as DIBL, it's possible
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that the CMOS assembly spends more time with both
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the nMOS and pMOS transistors conducting current,
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which again would reduce the rate at which we
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can charge the output.
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The linear analysis that we typically perform rests on many
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levels of simplification. One of these levels ignores all but
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the capacitance of the transistors connected to the output
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to estimate a gate's output capacitance. However, depending
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on the situation, the capacitances of other transistors
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can play a role in the final output as well. This is
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the case for a NOR gate, specifically when it's being pulled
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down. It's possible that the ``top'' nMOS transistor of this
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gate was transparent while its output was high, which
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would charge the inner diffusion node between the two nMOs transistors
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to roughly $V_{GT}$. This contributes additional
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charge to the output, so it takes longer to pull down.
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In our specific situation, one input is constantly connected
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to $V_{dd}$, meaning that it is transparent. If this is
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the top input, it would allow charge into the shared nMOS
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diffusion region, causing a delay as described above.
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This is precisely what we see in the data: the NOR(1)
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column, in which the ``top`` transistor is connected
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to $V_dd$, the delays are higher.
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I used an alternative value of $\beta=1.5$. For the NAND gate, the logical effort
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increased (from 1.19 to 1.29). I believe
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that this is due to the resistances of the the pMOS transistors
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(which are affected by this change). In the NAND gate, there are
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two pMOS transistors in parallel. When beta is reduced from 2 to 1.5,
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their resistance goes up by a factor of $4/3$. Since the pull up time of the NAND
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gate is affected by the resistance of these transistors, and since this
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resistance now increased, it takes longer to pull up, leading to larger
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gate effort. This is further accentuated by the fact that one of the NAND
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inputs is tied to $V_{dd}$, which means the output is always pulled up
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via a single, higher-resistance transistor.
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\end{document}
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