58 lines
1.3 KiB
Plaintext
58 lines
1.3 KiB
Plaintext
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* File includes subcircuits and technology definitions
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.include ./SRAM_bits.cir
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*this cell emulates load from SRAM cells,
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* Number refers to the load from than number of cells
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.subckt memLoad ttt fff number=254
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Xnt ttt gnd dead nn ww='number*5'
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Xnf fff gnd dead nn ww='number*5'
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.ends memLoad
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*********begin: topLevel*****
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* Parameters
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.global gnd vdd
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.param gnd=0
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*********begin: topLevel*****
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.param per = 2ns
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.param dataLead=per*0.1
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.param lw=1800
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.param wirew=12
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vdd vdd 0 'supply'
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Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50
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Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1
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Xdii din dat1 period='per' start='per' total=4 duty=2 sz=30
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Xwr bt1 bf1 din rdw clk write1
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Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
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Xmd1 bt2 bf2 memLoad number=16
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Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'
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Xmd2 bt3 bf3 memLoad number=16
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Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
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Xmd3 bt4 bf4 memLoad number=16
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Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
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Xmd4 btt bff memLoad number =15
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Xla btt bff clk mem1
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Xrd btt bff set rst rdw clk readSub
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Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
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.ic V(la:tt)=0 V(la:ff)=1
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.ic V(bt2)=1
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.tran 1p 'per*20'
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