88 lines
5.2 KiB
TeX
88 lines
5.2 KiB
TeX
\documentclass{article}
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\usepackage[margin=1in]{geometry}
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\usepackage{graphicx}
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\usepackage{amsmath}
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\title{Final Project Report}
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\author{Danila Fedorin}
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\begin{document}
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\maketitle
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\section*{General Design and Considerations}
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The goal of this assignment was to create a 256-byte SRAM memory unit. In order
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to minimize wire delays, I chose to split each bit into \textbf{4 columns of 64 SRAM cells
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each}. This was motivated by the following factors:
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\begin{itemize}
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\item \emph{Larger} columns were eliminated due to the high cost of interconnect.
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Even large write blocks were not able to charge the ``far ends'' of the wire
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at shorter clock cycles. Increasing wire width did not help; although resistance
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decreased, the capacitance increased, leading to small net gains. Thus, I made
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the decision to shrink the columns as much as possible. However...
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\item \emph{Smaller} columns became a routing challenge. Even with a 4-column split,
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to properly connect each cell of the SRAM column, the SRAM cells themselves need
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to accomodate an additional three \textsc{Wl} lines. Due to the pitch requirements
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on metals three and four, this is the upper limit (for reasonably sized cells).
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Alternatives included splitting the decoder into pieces, but for large numbers
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of columns, this meant that the decoder signal traveled through significant amounts
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of wire, and was thus slower.
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\end{itemize}
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For each of the 4 64-bit columns, I attached separate read and write blocks. However,
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my placement of the write block was unorthodox. I observed that, although the write block
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is perfectly capable of quickly manipulating the bitlines close to it, the changes
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to the wires take too long to propagate through to the end. I addressed this with two separate
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changes:
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\begin{itemize}
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\item I added \textbf{additional precharge transistors} along the column, a total of 4.
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Each was sized at $5\lambda$, much like the SRAM transistors themselves. When the clock
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was low, these PMOS transistors became transparent, and helped precharge the bitlines faster.
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Doing so helped avid hysteresis. However, this did not help with writing during high clock,
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so...
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\item I also \textbf{placed the write block in the middle of the column}. This increased the distance
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between my furthest SRAM cell and the read block (since the write block now contributed to wire
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length). However, this made it significantly easier to drive the entire length of the wire,
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which was my main bottleneck. This was because the maximum distance from the write
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block to any cell in the column was halved. Since my read circuit continued to work in this
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configuration, I did not place it in the middle of the column, as that would needlessly
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increase the length of the wires.
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\end{itemize}
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This led to the configuration shown in Figure \ref{fig:top-design}. To simulate this design, I placed
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a memory cell at the very top of my column, which is the furthest spot from both the read and write
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circuit. I also split the wire into 4 equally-sized fragments, each with resistance $\frac{R}{4}$ and
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capacitance $\frac{C}{4}$. Between each fragment, I added the aforementioned $5\lambda$ precharge
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transistors, as well as 16 always-off $5\lambda$ transistors, which simulated the remaining memory cells.
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I also placed \textsc{Din}, \textsc{Ad0}, and \textsc{Rwt} behind the default-sized flip-flops
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attached to the clock to simulate something like a pipeline stage. My overall design is shown
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in figure \ref{fig:top-design-sim}.
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\pagebreak
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\section*{Performance Results}
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I made three measurements of my performance.
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\begin{itemize}
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\item Without flip-flopping my inputs and outputs, I was able to clock my design around
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950\textit{ps}.
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\item With flip-flops on my inputs (but not on my output), I was able to clock my design
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around 1.24\textit{ns}. However, at this delay, the output of the gate came in very close to
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the falling edge of the clock.
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\item With flip-flops on my inputs and my outputs, I was able to clock my design at 2.6\textit{ns}.
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This significant delay was to allow enough setup time for the flip flop.
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\end{itemize}
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%
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Two factors lead to these upper limits.
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%
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\begin{itemize}
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\item \textit{Write capacitance} makes it increasingly difficult to overwrite the value
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in the cell. Clocking my design any faster than 950\textit{ps} or 1.24\textit{ns}
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(depending on the case) leads my cell to \textit{almost} flip, but not resolve correctly.
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I have found no way to work around these limits once my wire was properly sized, and my
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write block was placed in the middle of the column.
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\item \textit{Flop, decoder, and read delays} are the major limitation when both the inputs
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and the outputs of the circuit are connected to flip flops. Even though the output
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of the read block is correct, it doesn't arrive fast enough to be captured by the next cycle.
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Furthermore, in some cases, the signal to open a memory cell arrives later than the
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\textsc{Trig} signal for the senseamp, making it read too early and thus output the incorrect value.
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\end{itemize}
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\end{document}
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