A CPU written in SystemVerilog for ECE 271.
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/**
* CPU-specific memory. raddr is used for reading,
* while wen (write enable), waddr, and in are used in combination to write.
* Reads are performed immediately, but writes are performed on
* positive clock edge. Reset clears the memory to 0.
*/
module memory #(width=32)
(input logic [7:0] raddr, waddr,
input logic [width-1:0] in,
input logic clk, wen, reset,
output logic [width-1:0] out);
logic [width-1:0] data [0:255];
always_ff@(posedge clk)
if(reset) begin
data <= '{default: 0};
end else begin
if(wen) begin
data[waddr] <= in;
end
end
assign out = data[raddr];
endmodule