A CPU written in SystemVerilog for ECE 271.
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Danila Fedorin 5c24d2e464 Update code with new edge detector. 3 years ago
tasm Add an assembly program to demonstrate reading. 3 years ago
alu.sv Add comments. 3 years ago
assembler.cr Add help to assembler. 3 years ago
cpu.sv Add comments. 3 years ago
cpu_controller.sv Update code with new edge detector. 3 years ago
edge_detector.sv Update code with new edge detector. 3 years ago
memory.sv Add comments. 3 years ago
mux2.sv Add comments. 3 years ago
mux4.sv Add comments. 3 years ago
register.sv Add comments. 3 years ago
spi_encoder.cr Add script to generate SPI DO files. 3 years ago
spi_slave.sv Update code with new edge detector. 3 years ago