9 lines
214 B
Systemverilog
9 lines
214 B
Systemverilog
/* A two-input multiplexer.
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*/
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module mux2 #(width=32)
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(input logic [width-1:0] left, right,
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input logic select,
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output logic [width-1:0] out);
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assign out = select ? right : left;
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endmodule
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