A CPU written in SystemVerilog for ECE 271.
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/**
* Register file as used by the CPU. Has two read addresses so that
* two-register instructions can be performed in one cycle. Just like memory,
* reading is asynchronous, while writes occur on positive clock edge.
* wen, waddr, and in are used to write to register memory.
*/
module registers #(width=32)
(input logic [2:0] raddr1, raddr2, waddr,
input clk, wen, reset,
input logic [width-1:0] in,
output logic [width-1:0] out1, out2);
logic [width-1:0] data [0:7];
always_ff@(posedge clk)
if (reset) begin
data <= '{default: 0};
end else begin
if(wen) data[waddr] <= in;
end
assign out1 = data[raddr1];
assign out2 = data[raddr2];
endmodule