You can not select more than 25 topics
Topics must start with a letter or number, can include dashes ('') and can be up to 35 characters long.
173 lines
7.2 KiB
173 lines
7.2 KiB
\documentclass{article}


\usepackage[margin=1in]{geometry}


\usepackage{graphicx}


\usepackage{amsmath}


\title{Homework 5}


\begin{document}


\maketitle


\section*{Q1}


\subsection*{Part a}


In lecture, Scott said that he specifically wants the top path optimized. In this


case, we insert a unit inverter at the fork in front of the bottom path.




The minimal delay depends on the intrinsic and incremental delay of


each gate. We thus assume the conditions of part c, that is,


that the intrinsic and incremental delay are both 30ps.




Solving for the ideal number of stages involves computing $\rho$. This, in turn, is


done by solving the equation: $p_\text{inv} + \rho(1\ln\rho) = 0$. Knowing that


the intrinsic and parasitic delays are the same, we set $p_\text{inv}=1$, and


thus obtain $\rho=3.59$. To find the ideal number of stages, we now need


to compute $\log_\rho$ of our path effort F.




To comptue F, we must first determine the logical effort of each of the gates


used in the circuit. With a $\beta$ of 1.2, we get $g=\frac{3.2}{2.2}$ for the


NAND gate, and $\frac{3.4}{2.2}$ for the NOR gate. Then, we have:




\begin{equation*}


\begin{aligned}


G &= \left(\frac{3.2}{2.2}\right)\left(\frac{3.4}{2.2}\right) \\


H &= \frac{1000}{2} = 500 \quad \text{(for the top path)}


\end{aligned}


\end{equation*}




In this case, we have a branching effort of




\begin{equation*}


2\left(\frac{1+s_{3,t}}{s_{3,t}}\right) \approx 2\times 1 = 2


\end{equation*}




We thus compute the following total effort:




\begin{equation*}


\begin{aligned}


F &= \left(\frac{3.2}{2.2}\right)\left(\frac{3.4}{2.2}\right)\left(\frac{1000}{2}\right)2 \approx 2247 \\


\hat{N} &= \log_\rho F \approx 6


\end{aligned}


\end{equation*}




Here, assume the polarity of the signal doesn't matter, so that we really can insert an odd number


of inverters. While adding inverters, we observe that we can transform the NOR gate into a NAND


gate, thereby reducing the path effort slightly. Thus, we place one inverter right after the fork


on the top path, and two inverters on the other side of the formerlyNORnowNAND gate. Recomputing


total effort $F$ and stage effort $\hat{f}$:




\begin{equation*}


\begin{aligned}


F &= \left(\frac{3.2}{2.2}\right)\left(\frac{3.2}{2.2}\right)\left(\frac{1000}{2}\right)2 \approx 2116 \\


\hat{f} &\approx 3.58


\end{aligned}


\end{equation*}




The parasitic delays of the two gates (relative to the inverter) are, even with $\beta=1.2$, stil


equal to 2. Thus, we have a total delay of:




\begin{equation*}


6\times 30 \times\hat{f} + 8 \times 30 \approx 885\textit{ps}


\end{equation*}




\pagebreak


We can also compute gate sizes.




\begin{equation*}


\begin{aligned}


s_{6,t} &= 1000/\hat{f} \approx 279 \\


s_{5,t} &= 1000/\hat{f}^2 \approx 77.9 \\


s_{4,t} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^3 \approx 31.6 \\


s_{3,t} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^4 \approx 8.83 \\


s_{2} &= \left(\frac{3.2}{2.2}\right)^2 1000/\hat{f}^5 \approx 3.58 \\


s_{1} &= 2\left(\frac{3.2}{2.2}\right)^2 1000/\hat{f}^6 \approx 2


% (3.4/2.2)(3.2/2.2)*1.5


\end{aligned}


\end{equation*}




\subsection*{Part b}




The branching effort $B$ does not follow immediately from the circuit. However,


given the constraint that the two delays must be the same, we find that


the size of the top NOR gate must be twice the size of the bottom NOR


nly


gate. This, in turn, leads to a branching effort (again, for the top path)


of $1.5$. Thus, we get:




\begin{equation*}


\begin{aligned}


B &= 2\left(\frac{3}{2}\right) \\


F &= \left(\frac{3.2}{2.2}\right)\left(\frac{3.2}{2.2}\right)\left(\frac{1000}{2}\right)2\left(\frac{3}{2}\right) \approx 3174 \\


\hat{N} &= \log_\rho F \approx 6


\end{aligned}


\end{equation*}




Here, assume the polarity of the signal doesn't matter, so that we really can insert an odd number


of inverters at the end of each branch. The sizes are thus:




\begin{equation*}


\begin{aligned}


s_{6,t} &= 1000/\hat{f} \approx 261 \\


s_{6,b} &= 500/\hat{f} \approx 131 \\


s_{5,t} &= 1000/\hat{f}^2 \approx 68.0 \\


s_{5,b} &= 1000/\hat{f}^2 \approx 34.0 \\


s_{4,t} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^3 \approx 25.8 \\


s_{4,b} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^3 \approx 12.9 \\


s_{3,t} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^4 \approx 6.73 \\


s_{3,t} &= \left(\frac{3.3}{2.2}\right)1000/\hat{f}^4 \approx 3.37 \\


s_{2} &= \left(\frac{3.2}{2.2}\right)^2 1000/\hat{f}^5 \approx 3.83 \\


s_{1} &= 2\left(\frac{3.2}{2.2}\right)^2 1000/\hat{f}^6 \approx 2


% (3.4/2.2)(3.2/2.2)*1.5


\end{aligned}


\end{equation*}




The calculation for total delay is the same, except that a different value of $\hat{f}$ is used.




\begin{equation*}


6\times 30 \times\hat{f} + 8 \times 30 \approx 930\textit{ps}


\end{equation*}




\pagebreak


\subsection*{Part c}


See parts a and b for the respective delay calculations.




\subsection*{Part d}


The ratios of the PMOS and NMOS transistors are given by $\frac{\beta}{\beta+2}$ and $\frac{2}{\beta+2}$. For part a, since the size of the gate itself is 3.58, the sizes of the PMOS and NMOS are, respectively, 1.345 and 2.24. For part b, when the gate has a size of 3.83, the transistors themselves come in at 1.44 and 2.39.




\section*{Q2}


As far as I know, there's no way to guarantee the resolution of a metastable state in any amount of time. Metastability is resolved through random perturbations (however small), and thus there's technically possibility that it doesn't resolve one way or the other.




\section*{Q3}


With the ideal number of stages being 5, we can employ a trick. We need to insert two inverters;


if we do this right after the NOR gate, we can "push" one of the bubbles, turning the structure


into an inverter, followed by a NAND gate, followed by another inverter. The rest of the circuit


remains the same: a 4input NAND gate followed by an inverter. This way, we have a logical effort of:




\begin{equation*}


\begin{aligned}


G &= \left(\frac{4}{3}\right)\times 2 = \frac{8}{3} \\


H &= c \\


B &= 1


\end{aligned}


\end{equation*}


Then, the total delay is:


\begin{equation*}


\begin{aligned}


100\times5\times\left[\left(\frac{8}{3}\right)c\right]^{\frac{1}{5}} + 50\times (4+2+1+1+1) &= 2400 \\


\Rightarrow c &= 338


\end{aligned}


\end{equation*}




\section*{Q4}


A wire without repeaters has its delay increase quadratically with length. This is because both the


resistance and capacitance are proportional to length. On the other hand, wire delay increases


only linearly with repaters. In particular, the following equation is given in the book:


\begin{equation*}


t_{pd} = 1.81 \sqrt{\text{FO4} R_wC_w}l


\end{equation*}


Where l is the wire length.




\section*{Q5}


When nearby wires do not have the same signal as the wire itself, it effectively experiences


additional capacitance from the coupling. Thus, it becomes harder to drive the wire (since


more charge is effecitvely needed to change the voltage); this, in turn, increases delay.


In fact, it almost behaves as though the wire is connected to the nearby wires via a very


capacitive material; in that sense, it's \emph{almost} as if the branching effort is higher.




\end{document}


