52 lines
953 B
Plaintext
52 lines
953 B
Plaintext
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* File includes subcircuits and technology definitions
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.include ./SRAM_bits.cir
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*this cell emulates load from SRAM cells,
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* Number refers to the load from than number of cells
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.subckt memLoad ttt fff number=254
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Xnt ttt gnd dead nn ww='number*5'
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Xnf fff gnd dead nn ww='number*5'
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.ends memLoad
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*********begin: topLevel*****
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* Parameters
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.global gnd vdd
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.param gnd=0
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*********begin: topLevel*****
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.param per = 1ns
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.param lw=500
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.param wirew=3
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*DC supplies
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* make sure data signal is set up before clock signal triggers write
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* possible NOR rdw and Clk, and then maybe delay clk?
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* connect PMOS transistors to output of NOR gate, not directly to clk
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vdd vdd 0 'supply'
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Xclok clk dat1 period='per' start='per' total=1 duty=0.5 sz=120
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Xrdwr rdw dat1 period='per' start='per' total=2 duty=1
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Xdii dii dat1 period='per' start='per+0' total=3 duty=1
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Xwr bt0 bf0 dii gnd clk write1
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.tran 1p 15n
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