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Danila Fedorin 2021-03-17 12:21:35 -07:00
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@ -282,7 +282,7 @@ the vertical wires, \textsc{Bt} and \textsc{Bf}. This allowed me to use metal fo
\textsc{Wl} (access) signal. Since this was the only use of metal four, I had enough free \textsc{Wl} (access) signal. Since this was the only use of metal four, I had enough free
room to route thee additional \textsc{Wl} signals to the remaining three columns. room to route thee additional \textsc{Wl} signals to the remaining three columns.
My general principle for designing the layout was that, in an 8-bit, 4-column design, \textbf{a single My general principle for designing the layout was that, in an 12-bit, 4-column design, \textbf{a single
unit of height costs as much as 64 units of width}. Thus, I was fairly liberal with my layout's unit of height costs as much as 64 units of width}. Thus, I was fairly liberal with my layout's
width, but made sure to minimize the height of the design. The most significant bottleneck width, but made sure to minimize the height of the design. The most significant bottleneck
was the gate oxide ``poking out'' of the ends of the design. In total, I was able to achieve was the gate oxide ``poking out'' of the ends of the design. In total, I was able to achieve