Update todos

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Danila Fedorin 2021-03-16 19:02:06 -07:00
parent 8b9eabdec1
commit 4d4ceddcc6

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@ -1,5 +1,6 @@
* [x] Figure out the weird opAmp behavior
* [ ] Design cell with strict metal policies
* [ ] Add precharger version of memory cell (or explain how they compose)
* [ ] Test cell in the _middle_.
* [ ] Walk through the consequences of the read/write block being in the middle.
* [x] Design cell with strict metal policies
* [x] Add precharger version of memory cell (or explain how they compose)
* [x] Test cell in the _middle_.
* [x] Walk through the consequences of the read/write block being in the middle.
* [ ] Figure out what to do with flopped write block.