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1.9ns everywhere.

This commit is contained in:
Danila Fedorin 2021-03-17 12:19:33 -07:00
parent 71195df7c9
commit 6530e7ef8c
2 changed files with 6 additions and 4 deletions
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2
final/SRAM_bits.cir
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@ -268,7 +268,7 @@ Xh2 nn1 dot inv size='60'
.subckt decModel choose din clk size='20' .subckt decModel choose din clk size='20'
Xi1 nn1 din inv size='size' Xi1 nn1 din inv size='size'
* Here: stopped using i1 and just used din * Here: stopped using i1 and just used din
Xnal ww1 gnd din nnd2 size='size' Xnal ww1 gnd din nnd2 size='size*4'
Xnar nn2 vdd din nnd2 size='size' Xnar nn2 vdd din nnd2 size='size'
Xnrl ww2 nn2 vdd nor2 size='size*3' Xnrl ww2 nn2 vdd nor2 size='size*3'
Xnrr nn3 nn2 gnd nor2 size='size' Xnrr nn3 nn2 gnd nor2 size='size'

8
final/testBuffer.cir
View File

@ -21,10 +21,10 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel***** *********begin: topLevel*****
.param per = 1.34ns .param per = 1.9ns
.param dataLead=per*0.1 .param dataLead=per*0.1
.param lw=2200 .param lw=2200
.param wirew=14 .param wirew=12
vdd vdd 0 'supply' vdd vdd 0 'supply'
@ -55,7 +55,9 @@ Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
Xmd3 bt4 bf4 memLoad number=16 Xmd3 bt4 bf4 memLoad number=16
Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew' Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
Xmd4 bt3 bf3 memLoad number =16 Xmd4 bt3 bf3 memLoad number =16
Xla bt1 bf1 choose mem1 * Xla bt1 bf1 choose mem1
* Xla bt3 bf3 choose mem1
Xla btt bff choose mem1
Xrd btt bff set rst rdwf clk choose iReadSub Xrd btt bff set rst rdwf clk choose iReadSub
Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect