Merge branch 'master' of dev.danilafe.com:ECE-571/Labs
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* [x] Add precharger version of memory cell (or explain how they compose)
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* [x] Add precharger version of memory cell (or explain how they compose)
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* [x] Test cell in the _middle_.
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* [x] Test cell in the _middle_.
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* [x] Walk through the consequences of the read/write block being in the middle.
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* [x] Walk through the consequences of the read/write block being in the middle.
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* [ ] Figure out what to do with flopped write block.
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* [x] Figure out what to do with flopped write block.
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* [ ] Test data close to write block (it pulls up past clock low!)
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* [ ] Drive wires to zero?
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final/toplevel_design.png
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