Add Scott's various test files.

final/testBuffer.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 20ns
+.param dataLead=500ps
+.param lw=1000
+.param wirew=12
+
+vdd vdd 0 'supply'
+
+Xclok clk               dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=50
+Xrdwr rdw               dat1 period='per' start='2*per'        total=2 duty=1
+Xdii din                dat1 period='per' start='per'          total=4 duty=2   sz=30
+
+
+
+Xwr bt1 bf1 din rdw clk write1
+Xw1 bt1 btt bf1 bff     wire_dual len='lw' wid='wirew'
+Xmd btt bff             memLoad number =254
+Xla btt bff clk         mem1
+Xrd btt bff set rst rdw clk readSub
+Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
+.ic V(la:tt)=0 V(la:ff)=1
+.ic V(bt2)=1
+.tran 1p 'per*10'
+
+
+
+
+
+

final/testDecoder.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 5ns
+.param lw=500
+.param wirew=3
+
+
+*DC supplies
+vdd vdd 0 'supply'
+Xclok clk               dat1 period='per' start='per' total=1 duty=0.5 sz=120
+
+Xbit  ad0               dat1 period='per' start='0.5*per' total=3 duty=1
+Xde ope ad0 clk decModel size=20
+
+
+
+
+
+.tran 1p 25n
+
+
+
+
+
+

final/testMem.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 5ns
+.param lw=100
+.param wirew=3
+
+
+*DC supplies
+vdd vdd 0 'supply'
+Xclok clk               dat1 period='0.5*per' total=1 duty=0.5 sz=120
+Xdii dii                dat1 period='per' start='per' total=3 duty=1
+Xbit  ad0               dat1 period='per' start='0.5*per' total=3 duty=1
+Xde   ope ad0 clk decModel size=20
+
+* hardwire rdw signal to gnd
+Xwr bt0 bf0 dii gnd clk write1
+Xw0 bt0 bt1 bf0 bf1     wire_dual len='lw' wid='wirew'
+
+* Place memory cell at end of wire
+* First make sure it works with short wire and few memory cells
+* View on plotter
+*v(ope), v(dii)
+*v(la:ff) v(la:tt)
+*v(bf1) and v(bt1)
+Xla bt1 bf1 ope         mem1 m=1
+Xmd bt1 bf1             memLoad number =254
+
+
+
+ *14.462274109131130
+
+
+.tran 1p 50n
+
+
+
+
+
+

final/testRead.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 3n
+.param lw=5000
+.param wirew=3
+
+
+*DC supplies
+vdd vdd 0 'supply'
+
+Xclok clk               dat1 period='per' start='per' total=1 duty=0.5 sz=120
+Xrdwr rdw               dat1 period='per' start='per' total=2 duty=1
+Xdii dii                dat1 period='per' start='per' total=3 duty=1
+
+
+* vary
+.param dip=0.05
+Vt bt2  0  PULSE('supply''supply-dip' 'per' 10p 10p '2*per' '4*per')
+Vf bf2  0  PULSE('supply-dip''supply' 'per' 10p 10p '2*per' '4*per')
+
+Xbit  ad0               dat1 period='per' start='0.5*per' total=3 duty=1
+Xde ope ad0 clk decModel size=20
+
+
+* Xrd bt2 bf2 dot vdd clk read1
+Xrd bt2 bf2 set rst vdd clk readSub
+
+
+.ic v(dot)=0
+
+
+
+.tran 1p 50n
+
+
+
+
+
+

final/testSRAM.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 100ns
+.param lw=500
+.param wirew=3
+
+
+*DC supplies
+vdd vdd 0 'supply'
+Xclok clk               dat1 period='0.5*per' total=1 duty=0.5 sz=120
+Xrdwr rdw               dat1 period='per' start='per' total=2 duty=1
+*Vrdw rdw 0 'supply'
+Xbit  ad0               dat1 period='per' start='per' total=3 duty=1
+Xdii dii              dat1 period='4*per' total=1 duty=0.5 sz=120
+Xacc acc                dat1 period='per' start='per+10ps' total=2 duty=1
+
+*
+Xwr bt0 bf0 dii rdw clk write1
+Xw0 bt0 bt1 bf0 bf1     wire_dual len='lw' wid='wirew'
+Xla bt1 bf1 ope mem1
+Xmd bt1 bf1             memLoad number =1
+
+Xw1 bt1 bt2 bf1 bf2     wire_dual len='lw' wid='wirew'
+Xrd bt2 bf2 dot rdw clk read1
+
+Xde ope ad0 clk decModel size=10
+
+
+
+.tran 1ps 1600ns
+
+
+
+
+
+

final/testWrite.cir

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+
+
+* File includes subcircuits and technology definitions
+.include ./SRAM_bits.cir
+
+
+*this cell emulates load from SRAM cells,
+* Number refers to the load from than number of cells
+.subckt memLoad ttt fff number=254
+Xnt ttt gnd dead nn ww='number*5'
+Xnf fff gnd dead nn ww='number*5'
+.ends memLoad
+
+
+
+
+*********begin: topLevel*****
+
+* Parameters
+.global gnd vdd
+.param gnd=0
+
+
+*********begin: topLevel*****
+.param per = 1ns
+.param lw=500
+.param wirew=3
+
+
+*DC supplies
+
+* make sure data signal is set up before clock signal triggers write
+* possible NOR rdw and Clk, and then maybe delay clk?
+* connect PMOS transistors to output of NOR gate, not directly to clk
+
+
+vdd vdd 0 'supply'
+Xclok clk               dat1 period='per' start='per' total=1 duty=0.5 sz=120
+Xrdwr rdw               dat1 period='per' start='per' total=2 duty=1
+Xdii dii                dat1 period='per' start='per+0' total=3 duty=1
+
+Xwr bt0 bf0 dii gnd clk write1
+
+
+.tran 1p 15n
+
+
+
+
+
+