ECE-571/Labs
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

1.33ns with flip flops and bug mitigation

Browse Source
This commit is contained in:
Danila Fedorin 2021-03-16 16:30:28 -07:00
parent e077bb9071
commit 8b9eabdec1
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
final/SRAM_bits.cir
View File

@ -41,8 +41,8 @@ Xf lf rf wire len='len' wid='wid'
.subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10 .subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10
Xt lt rt wire len='len' wid='wid' Xt lt rt wire len='len' wid='wid'
Xf lf rf wire len='len' wid='wid' Xf lf rf wire len='len' wid='wid'
Xpt rt clk vdd pp ww='ww*4' Xpt rt clk vdd pp ww='ww*2'
Xpf rf clk vdd pp ww='ww*4' Xpf rf clk vdd pp ww='ww*2'
.ends .ends
.subckt nn d g s ww=100 .subckt nn d g s ww=100

6
final/testBuffer.cir
View File

@ -21,7 +21,7 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel***** *********begin: topLevel*****
.param per = 1.35ns .param per = 1.33ns
.param dataLead=per*0.1 .param dataLead=per*0.1
.param lw=2000 .param lw=2000
.param wirew=14 .param wirew=14
@ -30,8 +30,8 @@ vdd vdd 0 'supply'
Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300 Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300 Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300
Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=300 Xrdwr rdw dat1 period='3*per' start='2*per' total=2 duty=1 sz=300
Xdii din dat1 period='per' start='per' total=4 duty=2 sz=300 Xdii din dat1 period='3*per' start='per' total=4 duty=2 sz=300
Xinv1 clkb1 clk inv Xinv1 clkb1 clk inv
Xinv2 clkb2 clkb1 inv Xinv2 clkb2 clkb1 inv