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Update to use new wire model's characteristics.

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This commit is contained in:
Danila Fedorin 2021-03-17 13:07:33 -07:00
parent ff0edb93bb
commit d8f4a272e3
1 changed files with 3 additions and 3 deletions
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6
final/testBuffer.cir
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@ -21,10 +21,10 @@ Xnf fff gnd dead nn ww='number*5'
*********begin: topLevel*****
.param per = 1.9ns
.param per = 1.3ns
.param dataLead=per*0.1
.param lw=2200
.param wirew=12
.param wirew=14
vdd vdd 0 'supply'
@ -46,7 +46,7 @@ Xrdwff rdwf rdw clk flop
Xrotff dotf dot clk flop
Xdec choose adf clk decModel
Xwr bt3 bf3 dinf rdwf clkb6 iWrite1
Xwr bt3 bf3 dinf rdwf adf clkb6 iWrite1
Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
Xmd1 bt2 bf2 memLoad number=15
Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'