Add some minor additional sections to report.

final/SRAM_bits.cir

@@ -26,8 +26,8 @@
 
 
 .subckt wire iot iof len=10 wid=10
-.param rr=0.8
-.param cc = '200e-15'
+.param rr=0.4
+.param cc = '100e-15'
 rt iot iof 'rr*len*50/(wid)'
 cf iof  0  'cc*len*wid*50/1e6'
 
@@ -179,7 +179,7 @@ Xpct btt clk vdd pp ww='100'
 Xpcf bff clk vdd pp ww='100'
 .ends write1
 
-.subckt iWrite1 btt bff dii rwt clk
+.subckt iWrite1 btt bff dii rwt en clk
 * TODO: sizes
 Xclk clkb clk inv size='40'
 Xdii diib dii inv size='40'

final/report.tex

@@ -101,9 +101,15 @@ of length to this number, to a total of roughly $2200\lambda$.
 
 \pagebreak
 \section{Performance Results}
-I was able to clock my design at $1.9\textit{ns}$.
+I was able to clock my design at \textbf{$1.3\textit{ns}$}.
 %
-Two factors lead to these upper limits. 
+I realize that this isn't as fast as everyone else, but I ask that you take
+into consideration the fact that \textbf{I was working with the old wire model}
+until about an hour before the final due date (since I didn't know the wire model changed).
+If I knew earlier, I'd have more time to optimize my design for the timings associated
+with the new model.
+%
+Two factors lead to this upper limit.
 %
 \begin{itemize}
     \item \textit{Write capacitance} makes it increasingly difficult to overwrite the value
@@ -353,6 +359,27 @@ space incurred, an entire column is approximately $100\lambda$ wide.
 \label{fig:layout-arrayed}
 \end{figure}
 
+\pagebreak
+\section{Further Design Ideas}
+I discovered -- from other people in the class -- that an 8-column design was plausible.
+Unfortunately, I was only convinced a day or so before the project was due, which did not give me
+enough time to redesign my SRAM. I have seen students successfully using
+the 8-column design by sharing \textsc{Wl} wires for each 'row', and using
+the remaining 3 bits to enable and disable the write block. Since reading does
+not change the cell value, this is a viable approach; all 8 columns would ``read''
+(except during writing, in which 7 columns would read and 1 would write). As
+long as a proper address selection mechanism is implemented into the read collector
+circuit (which at present cannot handle concurrent reads), this would work just
+fine, albeit at the expense of added power consumption (from draining and re-charging
+7 extra wires). This design, combined with my idea of placing the write block
+in the middle of the column, can lead to very short effective wire lengths. If
+I was to approach this project again, that's what I would try.
+
+\section{Acknowledgements}
+Reed's aforementioned idea of sharing well contacts between adjacent cells
+played a part in my design. Also, without the other students in the class
+Discord, I would not have known to use the ``better'' wire model at all.
+
 \pagebreak
 \bibliographystyle{unsrt}
 \bibliography{bibliography}

final/testBuffer.cir

@@ -21,10 +21,10 @@ Xnf fff gnd dead nn ww='number*5'
 
 
 *********begin: topLevel*****
-.param per = 1.9ns
+.param per = 1.3ns
 .param dataLead=per*0.1
 .param lw=2200
-.param wirew=12
+.param wirew=14
 
 vdd vdd 0 'supply'
 
@@ -46,7 +46,7 @@ Xrdwff rdwf rdw clk flop
 Xrotff dotf dot clk flop
 Xdec choose adf clk decModel
 
-Xwr bt3 bf3 dinf rdwf clkb6 iWrite1
+Xwr bt3 bf3 dinf rdwf adf clkb6 iWrite1
 Xw1 bt1 bt2 bf1 bf2  clk   wire_precharge len='lw/4' wid='wirew'
 Xmd1 bt2 bf2 memLoad number=15
 Xw2 bt2 bt3 bf2 bf3  clk   wire_precharge len='lw/4' wid='wirew'