124 lines
3.1 KiB
Plaintext
124 lines
3.1 KiB
Plaintext
*Assignment:
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* Find the measured logical effort for a two input NOR gate, and a two input NAND gate
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* empirically by taking the ratio of slopes for delay vs fanout for the logic gates
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* and an inverter.
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* Plot delay as a function of fanout for an inverter, 2 input Nor and Nand.
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* measure the slopes of these lines.
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* ratio the slopes for Nand and Nor to that of the inverter
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* how does that compare to back of envelope calculation for this technology?
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***** long channel VTP = -0.9, VTN = 0.8 *****
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* .include modelcard/1um.pm
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* .param supply = 5
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* .param ll = 1u
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****** 50nm models***
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* .include ./modelcard/50nm.pm
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* .param supply =1
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* .param ll=50nm
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****** 16nm low power models***
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* .include ./modelcard/PTM_LP/16nm.pm
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* .param supply =0.9
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* .param ll=16nm
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****** 16nm high peformance models***
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.include ./modelcard/PTM_HP/16nm.pm
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.param supply =0.7
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.param ll=16nm
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.subckt nn d g s ww=100nm
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mnfet d g s 0 nmos L=ll w=ww
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.ends
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.subckt pp d g s ww=100nm
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mpfet d g s vdd pmos L=ll w=ww
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.ends
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.subckt inv out inn size=100n beta=2
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XPP out inn vdd pp ww='size*beta/(beta+1)'
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XNN out inn 0 nn ww='size/(beta+1)'
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.ENDS inv
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.subckt nd2 out in0 in1 size=100n beta=2
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Xp0 out in0 vdd pp ww='beta*size/(beta+2)'
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Xp1 out in1 vdd pp ww='beta*size/(beta+2)'
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Xn0 out in0 nnn nn ww='2*size/(beta+2)'
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Xn1 nnn in1 gnd nn ww='2*size/(beta+2)'
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.ends nd2
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.subckt no2 out in0 in1 size=100n beta=2
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Xp0 nnn in0 vdd pp ww='2*beta*size/(2*beta+1)'
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Xp1 out in1 nnn pp ww='2*beta*size/(2*beta+1)'
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Xn0 out in0 gnd nn ww='size/(2*beta+1)'
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Xn1 out in1 gnd nn ww='size/(2*beta+1)'
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.ends no2
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.subckt dut out inn size = 10 bb = 1.5
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* xdut out inn inv size='size' beta='bb'
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* Xnn2 out inn vdd nd2 size='size' beta='bb'
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* Xno2 out inn gnd no2 size='size' beta='bb'
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Xno2 out gnd inn no2 size='size' beta='bb'
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.ends dut
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*********begin: topLevel*****
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.ic v(n0)=0
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.param mm=1
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.param gg=100
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x0 n1 n0 dut size='gg*ll'
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x1 n2 n1 dut size='gg*ll'
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x2 n3 n2 dut size='gg*ll'
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x3 n4 n3 dut size='gg*ll'
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x4 n5 n4 dut size='gg*ll'
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x5 n6 n5 dut size='gg*ll'
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x6 n0 n6 dut size='gg*ll'
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x7 thr thr dut size='gg*ll'
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xl0 p1 n0 dut size={ll*gg*mm}
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xl1 p2 n1 dut size={ll*gg*mm}
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xl2 p3 n2 dut size={ll*gg*mm}
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xl3 p4 n3 dut size={ll*gg*mm}
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xl4 p5 n4 dut size={ll*gg*mm}
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xl5 p6 n5 dut size={ll*gg*mm}
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xl6 p0 n6 dut size={ll*gg*mm}
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* Parameters
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.global gnd vdd
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.param gnd=0
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*DC supplies
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vdd vdd 0 'supply'
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* this line directs the simulator to perform a transient analysis
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* .tran <timestep> <simulationLength>
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.tran 1p 40n
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* Below are measurment statements that direct the simulator to make the specified measurements and write the to *.log file
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* Search the *.log file for the names (ivdd, del10,del1, rtime, ftime) to find the results.
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* one can also measure these value in the waveform viewer
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.meas ivdd find i(vdd) at=1.8n
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.meas thresh find v(thr) at=1.8n
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.meas del10 trig v(n1) val='0.5*supply' cross =2 targ v(n1) val='0.5*supply' cross =12
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.meas del1 param = 'del10/70'
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.meas rtime trig v(n2) val= '0.1 * supply' rise = 2 targ v(n2) val = '0.9*supply' rise =2
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.meas ftime trig v(n2) val= '0.9 * supply' fall = 2 targ v(n2) val = '0.1*supply' fall =2
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