291 lines
7.0 KiB
Plaintext
291 lines
7.0 KiB
Plaintext
* This file contains all the subcircuits to be used in SRAM256.cir
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***** long channel VTP = -0.9, VTN = 0.8 *****
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*.include modelcard/1um.pm
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*.param supply = 5
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*.param ll = 1u
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****** 50nm models***
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.include ./modelcard/50nm.pm
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.param supply =1
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.param lambda=25nm
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.param ll='2*lambda'
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****** 16nm low power models***
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*.include ./modelcard/PTM_LP/16nm.pm
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*.param supply =0.9
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*.param ll=16nm
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****** 16nm high peformance models***
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*.include ./modelcard/PTM_HP/16nm.pm
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*.param supply =0.7
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*.param ll=16nm
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.subckt wire iot iof len=10 wid=10
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.param rr=0.4
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.param cc = '100e-15'
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rt iot iof 'rr*len*50/(wid)'
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cf iof 0 'cc*len*wid*50/1e6'
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.ends
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.subckt wire_dual lt rt lf rf len=10 wid=10
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Xt lt rt wire len='len' wid='wid'
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Xf lf rf wire len='len' wid='wid'
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.ends
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.subckt wire_precharge lt rt lf rf clk len=10 wid=10 ww=10
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Xt lt rt wire len='len' wid='wid'
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Xf lf rf wire len='len' wid='wid'
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Xpt rt clk vdd pp ww='ww*2'
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Xpf rf clk vdd pp ww='ww*2'
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.ends
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.subckt nn d g s ww=100
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mnfet d g s 0 nmos L=ll w='ww*ll'
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.ends
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.subckt pp d g s ww=100
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mpfet d g s vdd pmos L=ll w='ww*ll'
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.ends
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.subckt inv out inn size=30 beta=2
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XPP out inn vdd pp ww='size*beta/(beta+1)'
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XNN out inn gnd nn ww='size/(beta+1)'
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.ends
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.subckt nnd2 out in1 in0 size=30 beta=2
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Xap0 out in0 vdd pp ww='beta*size/(beta+2)'
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Xap1 out in1 vdd pp ww='beta*size/(beta+2)'
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Xan0 out in0 nng nn ww='2*size/(beta+2)'
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Xan1 nng in1 0 nn ww='2*size/(beta+2)'
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.ends nnd2
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.subckt nor2 out in1 in0 size=30 beta=2
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Xap0 ppi in0 vdd pp ww='2*beta*size/(2*beta+1)'
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Xap1 out in1 ppi pp ww='2*beta*size/(2*beta+1)'
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Xan0 out in0 0 nn ww='1*size/(2*beta+1)'
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Xan1 out in1 0 nn ww='1*size/(2*beta+1)'
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.ends nor2
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.subckt latch out inn clk clb size=15 beta=2
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Xn inn clk qin nn ww='5'
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Xp inn clb qin pp ww='10'
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Xfp qin ggg vdd pp ww='5'
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Xfn qin ggg gnd nn ww='5'
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Xi ggg qin inv size='size'
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Xo out ggg inv size='3*size'
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.ends latch
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.subckt flop qqq ddd clk
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Xinve clb clk inv
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Xflip int ddd clb clk latch
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Xflop qqq int clk clb latch
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.ends flop
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.subckt reg8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 clk
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x7 ot7 in7 clk flop
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x6 ot6 in6 clk flop
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x5 ot5 in5 clk flop
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x4 ot4 in4 clk flop
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x3 ot3 in3 clk flop
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x2 ot2 in2 clk flop
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x1 ot1 in1 clk flop
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x0 ot0 in0 clk flop
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.ends reg8
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.subckt dat1 out period=1ns start=1ns sz=50 total=5 duty=3
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V0 j0 0 PULSE('supply' 0 'start' 10p 10p 'duty*period-10ps' 'total*period')
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x7 out j0 inv size='sz'
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.ends dat1
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*generates different data stream on all eight channels, buffered output
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.subckt dat8 o7 o6 o5 o4 o3 o2 o1 o0 per=1ns start=1ns size=50
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V0 j0 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' 'per')
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V1 j1 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '2*per')
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V2 j2 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '3*per')
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V3 j3 0 PULSE(0 'supply' 'start' 10p 10p '0.5*per-10ps' '4*per')
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V4 j4 0 PULSE('supply' 0 'start' 10p 10p '0.5*per-10ps' '1*per')
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V5 j5 0 PULSE('supply' 0 'start' 10p 10p '1*per-10ps' '2*per')
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V6 j6 0 PULSE('supply' 0 'start' 10p 10p '1.5*per-10ps' '3*per')
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V7 j7 0 PULSE('supply' 0 'start' 10p 10p '2*per-10ps' '4*per')
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xb o7 o6 o5 o4 o3 o2 o1 o0 j7 j6 j5 j4 j3 j2 j1 j0 buf8 sz='size'
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.ends dat8
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.subckt buf8 ot7 ot6 ot5 ot4 ot3 ot2 ot1 ot0 in7 in6 in5 in4 in3 in2 in1 in0 sz=100
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x7 ot7 in7 inv size='sz'
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x6 ot6 in6 inv size='sz'
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x5 ot5 in5 inv size='sz'
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x4 ot4 in4 inv size='sz'
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x3 ot3 in3 inv size='sz'
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x2 ot2 in2 inv size='sz'
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x1 ot1 in1 inv size='sz'
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x0 ot0 in0 inv size='sz'
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.ends buf8
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.subckt nnd3 out in2 in1 in0 size=20 beta=2
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Xp0 out in0 vdd pp ww='beta*size/(beta+3)'
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Xp1 out in1 vdd pp ww='beta*size/(beta+3)'
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Xp2 out in2 vdd pp ww='beta*size/(beta+3)'
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Xn0 out in0 nn0 nn ww='3*size/(beta+3)'
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Xn1 nn0 in1 nn1 nn ww='3*size/(beta+3)'
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Xn2 nn1 in2 gnd nn ww='3*size/(beta+3)'
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.ends
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.subckt senseAmp ot1 ot0 in1 in0 eva size=40
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Xn0 ot0 in0 ot1 eva nnd3 size ='size'
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Xn1 ot1 in1 ot0 eva nnd3 size ='size'
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.ends senseAmp
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.subckt iSenseAmp ot1 ot0 in1 in0 eva size=40
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Xp1 ot1 eva vdd pp ww='size'
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Xp2 ot1 ot0 vdd pp ww='size'
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Xp3 ot0 eva vdd pp ww='size'
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Xp4 ot0 ot1 vdd pp ww='size'
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Xn1 ot1 ot0 nn1 nn ww='size'
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Xn2 ot0 ot1 nn0 nn ww='size'
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Xn3 nn1 in1 pd nn ww='size'
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Xn4 nn0 in0 pd nn ww='size'
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Xn5 pd eva gnd nn ww='size'
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.ends
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.subckt precharge charge rwtb clk diib
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Xrdi rdi rwtb diib nnd2
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Xnn chargeb clk rdi nnd2
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Xout charge chargeb inv
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.ends precharge
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.subckt write1 btt bff dii rwt clk
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* TODO: sizes
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Xclk clkb clk inv size='25'
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Xdii diib dii inv size='25'
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Xrwt rwtb rwt inv size='25'
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Xrwn dorw clkb rwt nor2 size='50'
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Xdt pdt dii gnd nn ww='100'
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Xdf pdf diib gnd nn ww='100'
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Xwt btt dorw pdt nn ww='100'
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Xwf bff dorw pdf nn ww='100'
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Xpcet pcet rwtb clk diib precharge
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Xpcef pcef rwtb clk dii precharge
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Xpct btt clk vdd pp ww='100'
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Xpcf bff clk vdd pp ww='100'
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.ends write1
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.subckt iWrite1 btt bff dii rwt en clk
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* TODO: sizes
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Xclk clkb clk inv size='40'
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Xdii diib dii inv size='40'
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Xrwt rwtb rwt inv size='40'
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Xrwn dorw clkb rwt nor2 size='110'
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Xdt pdt dii gnd nn ww='200'
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Xdf pdf diib gnd nn ww='200'
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Xwt btt dorw pdt nn ww='200'
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Xwf bff dorw pdf nn ww='200'
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Xpcet pcet rwtb clk diib precharge
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Xpcef pcef rwtb clk dii precharge
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Xpct btt pcet vdd pp ww='100'
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Xpcf bff pcef vdd pp ww='100'
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.ends write1
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.subckt read1 btt bff dot rwt clk
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Xnd trigger rwt clk nnd2
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Xinv triggerb trigger inv
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Xamp set reset btt bff triggerb senseAmp size='40'
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Xinv1 set1 set inv
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Xinv2 set2 set1 inv
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Xinv3 reset1 reset inv
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* Old setup:
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* Xp nn1 set2 vdd pp
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* Xn nn1 reset1 gnd nn
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* Xh1 dot nn1 inv
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* Xh2 nn1 dot inv
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Xp dot set2 vdd pp
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Xn dot reset1 gnd nn
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Xh1 dot nn1 inv
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Xh2 nn1 dot inv
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.ends read1
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.subckt readSub btt bff set rst rwt clk en
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Xnd trigger rwt en clk nnd3
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Xinv triggerb trigger inv size='40'
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Xamp set rst btt bff triggerb senseAmp size='200'
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.ends read1
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.subckt iReadSub btt bff set rst rwt clk en
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Xnd trigger rwt en clk nnd3
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Xinv triggerb trigger inv size='40'
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Xamp set rst btt bff triggerb iSenseAmp size='40'
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.ends read1
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.subckt readcollect dot set0 rst0 set1 rst1 set2 rst2 set3 rst3
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Xset01 set01 set0 set1 nnd2
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Xset23 set23 set2 set3 nnd2
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Xrst01 rst01 rst0 rst1 nnd2
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Xrst23 rst23 rst2 rst3 nnd2
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Xnset01 nset01 set01 inv
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Xnset23 nset23 set23 inv
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Xp01 nn1 nset01 vdd pp
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Xp23 nn1 nset23 vdd pp
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Xn01 nn1 rst01 gnd nn
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Xn23 nn1 rst23 gnd nn
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Xh1 dot nn1 inv size='60'
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Xh2 nn1 dot inv size='60'
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.ends readCollect
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.subckt decode2 o11 o10 o01 o00 di1 di0 df1 df0
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.ends
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.subckt decode_nor16
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.ends
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.subckt decode_nnd16
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.ends
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.subckt decode_16and1
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.ends decode_16and1
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.subckt dmux256 o255 o223 0012 o001 dt7 dt6 dt5 d4 dt3 dt1 dt0
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.ends dmux256
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.subckt decModel choose din clk size='20'
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Xi1 nn1 din inv size='size'
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* Here: stopped using i1 and just used din
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Xnal ww1 gnd din nnd2 size='size*4'
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Xnar nn2 vdd din nnd2 size='size'
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Xnrl ww2 nn2 vdd nor2 size='size*3'
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Xnrr nn3 nn2 gnd nor2 size='size'
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Xna2l ww3 gnd nn3 nnd2 size='size*15'
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Xna2r nn4 vdd nn3 nnd2 size='size'
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Xi2 nn5 nn4 inv size='size'
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Xnac nn6 nn5 clk nnd2 size='size'
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Xi3 choose nn6 inv size='size'
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.ends
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.subckt mem1 bt bf ope
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Xpt tt ff vdd pp ww='5'
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Xnt tt ff gnd nn ww='5'
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Xpf ff tt vdd pp ww='5'
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Xnf ff tt gnd nn ww='5'
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Xat bt ope tt nn ww='5'
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Xaf bf ope ff nn ww='5'
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.ends
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