Danila Fedorin f317a7e8da Add some minor additional sections to report.

2021-03-17 13:34:04 -07:00

..

amp.png

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2021-03-17 00:02:13 -07:00

decoder.png

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2021-03-17 00:02:13 -07:00

layout_arrayed_closeup.png

Add missing images.

2021-03-17 12:19:02 -07:00

layout_arrayed.png

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2021-03-17 12:19:02 -07:00

layout_single.png

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2021-03-17 12:19:02 -07:00

read_select.png

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2021-03-17 00:02:13 -07:00

report.tex

Add some minor additional sections to report.

2021-03-17 13:34:04 -07:00

SRAM_bits.cir

Size sense amp back to 40

2021-03-17 13:12:55 -07:00

SRAM.jelib

Add final SRAM design.

2021-03-17 12:19:17 -07:00

testBuffer.cir

Update to use new wire model's characteristics.

2021-03-17 13:07:33 -07:00

testDecoder.cir

Add Scott's various test files.

2021-03-09 19:15:28 -08:00

testMem.cir

Add Scott's various test files.

2021-03-09 19:15:28 -08:00

testRead.cir

Add Scott's various test files.

2021-03-09 19:15:28 -08:00

testSRAM.cir

Add Scott's various test files.

2021-03-09 19:15:28 -08:00

testWrite.cir

Add Scott's various test files.

2021-03-09 19:15:28 -08:00

todo.md

Add TODO.

2021-03-17 11:51:50 -07:00

toplevel_design.png

Add initial designs.

2021-03-16 18:32:56 -07:00

toplevel.png

Add initial designs.

2021-03-16 18:32:56 -07:00

write.png

Upload files to 'final'

2021-03-17 00:32:18 -07:00