71 lines
1.9 KiB
Plaintext
71 lines
1.9 KiB
Plaintext
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* File includes subcircuits and technology definitions
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.include ./SRAM_bits.cir
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*this cell emulates load from SRAM cells,
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* Number refers to the load from than number of cells
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.subckt memLoad ttt fff number=254
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Xnt ttt gnd dead nn ww='number*5'
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Xnf fff gnd dead nn ww='number*5'
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.ends memLoad
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*********begin: topLevel*****
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* Parameters
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.global gnd vdd
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.param gnd=0
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*********begin: topLevel*****
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.param per = 1.3ns
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.param dataLead=per*0.1
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.param lw=2200
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.param wirew=14
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vdd vdd 0 'supply'
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Xclok clk dat1 period='per' start='per+dataLead' total=1 duty=0.5 sz=300
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Xad ad dat1 period='per' start='per' total=1 duty=0.5 sz=300
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Xrdwr rdw dat1 period='per' start='2*per' total=2 duty=1 sz=300
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Xdii din dat1 period='per' start='per' total=4 duty=2 sz=300
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Xinv1 clkb1 clk inv
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Xinv2 clkb2 clkb1 inv
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Xinv3 clkb3 clkb2 inv
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Xinv4 clkb4 clkb3 inv size='300'
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Xinv5 clkb5 clkb4 inv
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Xinv6 clkb6 clkb5 inv size='300'
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Xad adf ad clk flop
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Xdinff dinf din clk flop
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Xrdwff rdwf rdw clk flop
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Xrotff dotf dot clk flop
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Xdec choose adf clk decModel
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Xwr bt3 bf3 dinf rdwf adf clkb6 iWrite1
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Xw1 bt1 bt2 bf1 bf2 clk wire_precharge len='lw/4' wid='wirew'
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Xmd1 bt2 bf2 memLoad number=15
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Xw2 bt2 bt3 bf2 bf3 clk wire_precharge len='lw/4' wid='wirew'
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Xmd2 bt3 bf3 memLoad number=16
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Xw3 bt3 bt4 bf3 bf4 clk wire_precharge len='lw/4' wid='wirew'
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Xmd3 bt4 bf4 memLoad number=16
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Xw4 bt4 btt bf4 bff clk wire_precharge len='lw/4' wid='wirew'
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Xmd4 bt3 bf3 memLoad number =16
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* Xla bt1 bf1 choose mem1
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* Xla bt3 bf3 choose mem1
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Xla btt bff choose mem1
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Xrd btt bff set rst rdwf clk choose iReadSub
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Xrc dot set rst vdd vdd vdd vdd vdd vdd readCollect
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.ic V(la:tt)=0 V(la:ff)=1
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.ic V(bt2)=1
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.tran 1p 'per*20'
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.meas tran dot_delay trig V(clk) val=0.8*supply rise=2 targ V(dot) val=0.8*supply rise=1
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