62 lines
1.1 KiB
Plaintext
62 lines
1.1 KiB
Plaintext
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* File includes subcircuits and technology definitions
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.include ./SRAM_bits.cir
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*this cell emulates load from SRAM cells,
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* Number refers to the load from than number of cells
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.subckt memLoad ttt fff number=254
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Xnt ttt gnd dead nn ww='number*5'
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Xnf fff gnd dead nn ww='number*5'
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.ends memLoad
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*********begin: topLevel*****
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* Parameters
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.global gnd vdd
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.param gnd=0
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*********begin: topLevel*****
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.param per = 5ns
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.param lw=100
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.param wirew=3
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*DC supplies
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vdd vdd 0 'supply'
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Xclok clk dat1 period='0.5*per' total=1 duty=0.5 sz=120
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Xdii dii dat1 period='per' start='per' total=3 duty=1
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Xbit ad0 dat1 period='per' start='0.5*per' total=3 duty=1
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Xde ope ad0 clk decModel size=20
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* hardwire rdw signal to gnd
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Xwr bt0 bf0 dii gnd clk write1
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Xw0 bt0 bt1 bf0 bf1 wire_dual len='lw' wid='wirew'
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* Place memory cell at end of wire
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* First make sure it works with short wire and few memory cells
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* View on plotter
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*v(ope), v(dii)
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*v(la:ff) v(la:tt)
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*v(bf1) and v(bt1)
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Xla bt1 bf1 ope mem1 m=1
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Xmd bt1 bf1 memLoad number =254
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*14.462274109131130
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.tran 1p 50n
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