Labs/final
Danila Fedorin 6f99879b8f Update electric files. 2021-03-17 09:00:29 -07:00
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SRAM.jelib Update electric files. 2021-03-17 09:00:29 -07:00
SRAM_bits.cir 1.33ns with flip flops and bug mitigation 2021-03-16 16:30:28 -07:00
amp.png Upload files to 'final' 2021-03-17 00:02:13 -07:00
decoder.png Upload files to 'final' 2021-03-17 00:02:13 -07:00
read_select.png Upload files to 'final' 2021-03-17 00:02:13 -07:00
report.tex Update report. 2021-03-16 23:25:30 -07:00
testBuffer.cir 1.33ns with flip flops and bug mitigation 2021-03-16 16:30:28 -07:00
testDecoder.cir Add Scott's various test files. 2021-03-09 19:15:28 -08:00
testMem.cir Add Scott's various test files. 2021-03-09 19:15:28 -08:00
testRead.cir Add Scott's various test files. 2021-03-09 19:15:28 -08:00
testSRAM.cir Add Scott's various test files. 2021-03-09 19:15:28 -08:00
testWrite.cir Add Scott's various test files. 2021-03-09 19:15:28 -08:00
todo.md Update 'final/todo.md' 2021-03-17 00:00:34 -07:00
toplevel.png Add initial designs. 2021-03-16 18:32:56 -07:00
toplevel_design.png Add initial designs. 2021-03-16 18:32:56 -07:00
write.png Upload files to 'final' 2021-03-17 00:32:18 -07:00