Danila Fedorin 0705df708e Prove that variables in a program all come from the program's code ... Signed-off-by: Danila Fedorin <danila.fedorin@gmail.com>		2024-03-10 16:41:21 -07:00
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Bundles	Use named modules to avoid having to pass redundant parameters	2024-03-09 21:46:15 -08:00
AboveBelow.agda	Format AboveBelow a bit better (round two)	2024-03-02 14:56:04 -08:00
FiniteMap.agda	Prove that the 'join' transformation is monotonic	2024-03-09 23:06:47 -08:00
FiniteValueMap.agda	Use named modules to avoid having to pass redundant parameters	2024-03-09 21:46:15 -08:00
IterProd.agda	Restore bundles in IterProd	2024-03-01 21:12:22 -08:00
Map.agda	Prove that variables in a program all come from the program's code	2024-03-10 16:41:21 -07:00
MapSet.agda	Prove that variables in a program all come from the program's code	2024-03-10 16:41:21 -07:00
Nat.agda	Rename some definitions in Nat and expose bundle	2024-02-11 20:56:21 -08:00
Prod.agda	Update with new changes to Agda	2024-03-03 16:44:10 -08:00
Unit.agda	Re-write the IterProd proofs to couple lattice and finite height lattice	2024-03-01 21:02:56 -08:00