VerilogCPU/mux4.sv

/**
 * A four-input multiplexer.
 */
module mux4 #(width=32)
			 (input logic [width-1:0] first, second, third, fourth,
			  input logic [1:0] select,
			  output logic [width-1:0] out);

	logic [width-1:0] lower, upper;

	mux2 lower_mux(
		.left(first),
		.right(second),
		.select(select[0]),
		.out(lower));
	mux2 upper_mux(
		.left(third),
		.right(fourth),
		.select(select[0]),
		.out(upper));

	mux2 final_mux(
		.left(lower),
		.right(upper),
		.select(select[1]),
		.out(out));
endmodule