26 lines
683 B
Systemverilog
26 lines
683 B
Systemverilog
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module alu #(width=32)
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(input logic [width-1:0] left, right,
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input logic [2:0] op,
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output logic [width-1:0] out);
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logic [width-1:0] selected_right, not_right;
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assign not_right = ~right;
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mux2 #(width) right_mux(
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.left(right),
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.right(not_right),
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.select(op[2]),
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.out(selected_right));
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logic [width-1:0] op_and, op_or, op_sum, op_slt;
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assign op_and = left & selected_right;
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assign op_or = left | selected_right;
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assign op_sum = left + selected_right + op[2];
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assign op_slt = op_sum[width-1];
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mux4 output_mux(
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.first(op_and),
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.second(op_or),
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.third(op_sum),
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.fourth(op_slt),
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.select(op[1:0]),
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.out(out));
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endmodule
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